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| UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Rev. 06 -- 9 March 2010 Product data sheet 1. General description The UJA1061 fail-safe System Basis Chip (SBC) replaces basic discrete components that are common in every Electronic Control Unit (ECU) with a Controller Area Network (CAN) and a Local Interconnect Network (LIN) interface. The fail-safe SBC supports all networking applications that control various power and sensor peripherals by using fault-tolerant CAN as the main network interface and LIN as a local sub-bus. The fail-safe SBC contains the following integrated devices: * ISO11898-3 compliant fault-tolerant CAN transceiver, interoperable with TJA1054, TJA1054A and TJA1055 * * * * * * LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3 Advanced independent watchdog Dedicated voltage regulators for microcontroller and CAN transceiver Serial peripheral interface (full duplex) Local wake-up input port Inhibit/limp-home output port In addition to the advantages of integrating these common ECU functions in a single package, the fail-safe SBC offers an intelligent combination of system-specific functions such as: * * * * Advanced low-power concept Safe and controlled system start-up behavior Advanced fail-safe system behavior that prevents any conceivable deadlock Detailed status reporting on system and subsystem levels The UJA1061 is designed to be used in combination with a microcontroller that incorporates a CAN controller. The fail-safe SBC ensures that the microcontroller is always started up in a defined manner. In failure situations, the fail-safe SBC will maintain microcontroller functionality for as long as possible to provide full monitoring and a software-driven fall-back operation. The UJA1061 is designed for 14 V single power supply architectures and for 14 V and 42 V dual power supply architectures. NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 2. Features and benefits 2.1 General Contains a full set of CAN and LIN ECU functions: CAN transceiver and LIN transceiver Voltage regulator for the microcontroller (3.3 V or 5.0 V) Separate voltage regulator for the CAN transceiver (5 V) Enhanced window watchdog with on-chip oscillator Serial Peripheral Interface (SPI) for the microcontroller ECU power management system Fully integrated autonomous fail-safe system Designed for automotive applications: Supports 14 V, 24 V and 42 V architectures Excellent ElectroMagnetic Compatibility (EMC) performance 8 kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) for off-board pins 6 kV ElectroStatic Discharge (ESD) protection IEC 61000-4-2 for off-board pins 60 V short-circuit proof CAN/LIN-bus pins Battery and CAN/LIN-bus pins are protected against transients in accordance with ISO 7637 Very low sleep current Supports remote flash programming via the CAN-bus Small 6.1 mm x 11 mm HTSSOP32 package with low thermal resistance 2.2 CAN transceiver ISO 11898-3 compliant fault-tolerant CAN transceiver Enhanced error signalling and reporting Dedicated low dropout voltage regulator for the CAN-bus: Independent from microcontroller supply Guarded by CAN-bus failure management Significantly improves EMC performance Partial networking option with global wake-up feature, allows selective CAN-bus communication without waking up sleeping nodes Bus connections are truly floating when power is off Ground shift detection 2.3 LIN transceiver LIN 2.0 compliant LIN transceiver Enhanced error signalling and reporting Downward compatible with LIN 1.3 and the TJA1020 UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 2 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 2.4 Power management Smart operating modes and power management modes Cyclic wake-up capability in Standby and Sleep modes Local wake-up input with cyclic supply feature Remote wake-up capability via the CAN-bus and LIN-bus External voltage regulators can easily be incorporated in the power supply system (flexible and fail-safe) 42 V battery-related high-side switch for driving external loads such as relays and wake-up switches Intelligent maskable interrupt output 2.5 Fail-safe features Safe and predictable behavior under all conditions Programmable fail-safe coded window and time-out watchdog with on-chip oscillator, guaranteeing autonomous fail-safe system supervision Fail-safe coded 16-bit SPI interface for the microcontroller Global enable pin for the control of safety-critical hardware Detection and detailed reporting of failures: On-chip oscillator failure and watchdog alerts Voltage regulator undervoltages CAN and LIN-bus failures (short-circuits and open-circuit bus wires) TXD and RXD clamping situations and short-circuits Clamped or open reset line SPI message errors Overtemperature warning ECU ground shift (two selectable thresholds) Rigorous error handling based on diagnostics 23 bits of access-protected RAM is available e.g. for logging of cyclic problems Reporting in a single SPI message; no assembly of multiple SPI frames needed limp-home output signal for activating application hardware in case system enters Fail-safe mode (e.g. for switching on warning lights) Fail-safe coded activation of Software development mode and Flash mode Unique SPI readable device type identification Software-initiated system reset UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 3 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 3. Ordering information Table 1. Ordering information Package Name UJA1061TW[1] HTSSOP32 Description Version plastic thermal enhanced thin shrink small outline package; 32 leads; SOT549-1 body width 6.1 mm; lead pitch 0.65 mm; exposed die pad Type number [1] UJA1061TW/5V0 is for the 5 V version; UJA1061TW/3V3 is for the 3.3 V version. 4. Block diagram BAT42 32 BAT MONITOR V1 UJA1061 4 V1 BAT14 27 V2 SYSINH V3 INH/LIMP 29 30 17 INH V1 MONITOR INTN WAKE TEST 7 18 16 CHIP TEMPERATURE SCK SDI SDO SCS 11 9 10 12 SPI GND SHIFT DETECTOR OSCILLATOR SBC FAIL-SAFE SYSTEM WAKE RESET/EN 20 V2 6 8 RSTN EN WATCHDOG RTLIN LIN TXDL RXDL GND 26 25 3 5 23 LIN FAULT TOLERANT CAN TRANSCEIVER BAT42 BAT42 V2 19 24 21 22 13 14 RTL RTH CANH CANL TXDC RXDC 001aad803 Fig 1. Block diagram UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 4 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 5. Pinning information 5.1 Pinning n.c. n.c. TXDL V1 RXDL RSTN INTN EN SDI 1 2 3 4 5 6 7 8 9 32 BAT42 31 RESERVED 30 V3 29 SYSINH 28 n.c. 27 BAT14 26 RTLIN 25 LIN 24 RTH 23 GND 22 CANL 21 CANH 20 V2 19 RTL 18 WAKE 17 INH/LIMP 001aad604 UJA1061 SDO 10 SCK 11 SCS 12 TXDC 13 RXDC 14 n.c. 15 TEST 16 Fig 2. Pin configuration 5.2 Pin description Table 2. Symbol n.c. n.c. TXDL V1 RXDL RSTN INTN EN SDI SDO SCK SCS TXDC RXDC n.c. TEST UJA1061_6 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description not connected not connected LIN transmit data input (LOW for dominant, HIGH for recessive) voltage regulator output for the microcontroller (3.3 V or 5 V depending on the SBC version) LIN receive data output (LOW when dominant, HIGH when recessive) reset output to microcontroller (active LOW; will detect clamping situations) interrupt output to microcontroller (active LOW; open-drain, wire-AND this pin to other ECU interrupt outputs) enable output (active HIGH; push-pull, LOW with every reset / watchdog overflow) SPI data input SPI data output (floating when pin SCS is HIGH) SPI clock input SPI chip select input (active LOW) CAN transmit data input (LOW for dominant; HIGH for recessive) CAN receive data output (LOW when dominant; HIGH when recessive) not connected test pin (should be connected to ground in application) (c) NXP B.V. 2010. All rights reserved. All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 06 -- 9 March 2010 5 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Pin description ...continued Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Description inhibit/limp-home output (BAT14 related, push-pull, default floating) local wake-up input (BAT42 related, continuous or cyclic sampling) CAN termination resistor connection; in case of a CANL bus wire error this line is terminated with a selectable impedance 5 V voltage regulator output for CAN; connect a buffer capacitor to this pin CANH bus line (HIGH in dominant state) CANL bus line (LOW in dominant state) ground CAN termination resistor connection; in case of a CANH bus wire error this line is terminated with a selectable impedance LIN bus line (LOW in dominant state) LIN-bus termination resistor connection 14 V battery supply input not connected system inhibit output (BAT42 related; e.g. for controlling external DC-to-DC converter) unregulated 42 V output (BAT42 related; continuous output, or Cyclic mode synchronized with local wake-up input) must be connected to ground (GND) 42 V battery supply input (connect this pin to BAT14 in 14 V applications) Table 2. Symbol INH/LIMP WAKE RTL V2 CANH CANL GND RTH LIN RTLIN BAT14 n.c. SYSINH V3 reserved BAT42 The exposed die pad at the bottom of the package allows better dissipation of heat from the SBC via the printed-circuit board. The exposed die pad is not connected to any active part of the IC and can be left floating, or can be connected to GND for the best EMC performance. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 6 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 6. Functional description 6.1 Introduction The UJA1061 combines all peripheral functions around a microcontroller within typical automotive networking applications into one dedicated chip. The functions are as follows: * * * * * * * * * * * * * Power supply for the microcontroller Power supply for the CAN transceiver Switched BAT42 output System reset Watchdog with Window mode and Time-out mode On-chip oscillator Fault-tolerant CAN and LIN transceivers for serial communication; suitable for 12 V and 42 V applications SPI control interface Local wake-up input Inhibit or limp-home output System inhibit output port Compatibility with 42 V power supply systems Fail-safe behavior 6.2 Fail-safe system controller The fail-safe system controller is the core of the UJA1061 and is supervised by a watchdog timer that is clocked directly by the dedicated on-chip oscillator. The system controller manages the register configuration and controls all internal functions of the SBC. Detailed device status information is collected and presented to the microcontroller. The system controller also provides the reset and interrupt signals. The fail-safe system controller is a state machine. The different operating modes and the transitions between these modes are illustrated in Figure 3. The following sections give further details about the SBC operating modes. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 7 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip mode change via SPI watchdog trigger Standby mode V1: ON SYSINH: HIGH CAN: on-line/on-line listen/off-line LIN: off-line watchdog: time-out/OFF INH/LIMP: HIGH/LOW/float EN: HIGH/LOW mode change via SPI mode change via SPI watchdog trigger Normal mode V1: ON SYSINH: HIGH CAN: all modes available LIN: all modes available watchdog: window INH/LIMP: HIGH/LOW/float EN: HIGH/LOW wake-up detected with its wake-up interrupt disabled OR mode change to Sleep with pending wake-up OR watchdog time-out with watchdog timeout interrupt disabled OR watchdog OFF and IV1 > I thH(V1) with reset option OR interrupt ignored > t RSTN(INT) OR RSTN falling edge detected OR V1 undervoltage detected flash entry enabled (111/001/111 mode sequence) OR illegal Mode register code OR mode change to Sleep with pending wake-up OR watchdog not properly served OR interrupt ignored > tRSTN(INT) OR RSTN falling edge detected OR V1 undervoltage detected OR illegal Mode register code mode change via SPI Sleep mode V1: OFF SYSINH: HIGH/float CAN: on-line/on-line listen/off-line LIN: off-line watchdog: time-out/OFF INH/LIMP: LOW/float RSTN: LOW EN: LOW init Normal mode via SPI successful wake-up detected OR watchdog time-out OR V3 overload detected Start-up mode V1: ON SYSINH: HIGH CAN: on-line/on-line listen/off-line LIN: off-line watchdog: start-up INH/LIMP: HIGH/LOW/float EN: LOW init Normal mode via SPI successful supply connected for the first time init Flash mode via SPI AND flash entry enabled t > t WD(init) OR SPI clock count < > 16 OR RSTN falling edge detected OR RSTN released and V1 undervoltage detected OR illegal Mode register code Restart mode V1: ON SYSINH: HIGH CAN: on-line/on-line listen/off-line LIN: off-line watchdog: start-up INH/LIMP: LOW/float EN: LOW t > t WD(init) OR SPI clock count < > 16 OR RSTN falling edge detected OR RSTN released and V1 undervoltage detected OR illegal Mode register code wake-up detected AND oscillator ok AND t > t ret leave Flash mode code OR watchdog time-out OR interrupt ignored > t RSTN(INT) OR RSTN falling edge detected OR V1 undervoltage detected OR illegal Mode register code watchdog trigger Flash mode V1: ON SYSINH: HIGH CAN: all modes available LIN: all modes available watchdog: time-out INH/LIMP: HIGH/LOW/float EN: HIGH/LOW Fail-safe mode V1: OFF SYSINH: HIGH/float CAN: on-line/on-line listen/off-line LIN: off-line watchdog: OFF INH/LIMP: LOW RSTN: LOW EN: LOW oscillator fail OR RSTN externally clamped HIGH detected > t RSTN(CHT) OR RSTN externally clamped LOW detected > t RSTN(CLT) OR V1 undervoltage detected > t V1(CLT) from any mode 001aad180 Fig 3. UJA1061_6 Main state diagram All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 8 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 6.2.1 Start-up mode Start-up mode is the `home page' of the SBC. This mode is entered when battery and ground are connected for the first time. Start-up mode is also entered after any event that results in a system reset. The reset source information is provided by the SBC to support different software initialization cycles that depend on the reset event. It is also possible to enter Start-up mode via a wake-up from Standby mode, Sleep mode or Fail-safe mode. Such a wake-up can originate either from the CAN-bus, the LIN-bus or from the local WAKE pin. On entering Start-up mode a lengthened reset time tRSTNL is observed. This reset time is either user-defined (via the RLC bit in the System Configuration register) or defaults to the value as given in Section 6.13.12. During the reset lengthening time pin RSTN is held LOW by the SBC. When the reset time is completed (pin RSTN is released and goes HIGH) the watchdog timer will wait for initialization. If the watchdog initialization is successful, the selected operating mode (Normal mode or Flash mode) will be entered. Otherwise the Restart mode will be entered. 6.2.2 Restart mode The purpose of the Restart mode is to give the application a second chance to start up, should the first attempt from Start-up mode fail. Entering Restart mode will always set the reset lengthening time tRSTNL to the higher value to guarantee the maximum reset length, regardless of previous events. If start-up from Restart mode is successful (the previous problems do not reoccur and watchdog initialization is successful), then the selected operating mode will be entered. From Restart mode this must be Normal mode. If problems persist or if V1 fails to start up, then Fail-safe mode will be entered. 6.2.3 Fail-safe mode Severe fault situations will cause the SBC to enter Fail-safe mode. Fail-safe mode is also entered if start-up from Restart mode fails. Fail-safe mode offers the lowest possible system power consumption from the SBC and from the external components controlled by the SBC. A wake-up (via the CAN-bus, the LIN-bus or the WAKE pin) is needed to leave Fail-safe mode. This is only possible if the on-chip oscillator is running correctly. The SBC restarts from Fail-safe mode with a defined delay tret, to guarantee a discharged V1 before entering Start-up mode. Regulator V1 will restart and the reset lengthening time tRSTNL is set to the higher value; see Section 6.5.1. 6.2.4 Normal mode Normal mode gives access to all SBC system resources, including CAN, LIN, INH/LIMP and EN. Therefore in Normal mode the SBC watchdog runs in (programmable) Window mode, for strictest software supervision. Whenever the watchdog is not properly served a system reset is performed. Interrupts from SBC to the host microcontroller are also monitored. A system reset is performed if the host microcontroller does not respond within tRSTN(INT). UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 9 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Entering Normal mode does not activate the CAN or LIN transceiver automatically. The CAN Mode Control (CMC) bit must be used to activate the CAN medium if required, allowing local cyclic wake-up scenarios to be implemented without affecting the CAN-bus. The LIN Mode Control (LMC) bit must be used to activate the LIN medium if required, allowing local cyclic wake-up scenarios to be implemented without affecting the LIN-bus. 6.2.5 Standby mode In Standby mode the system is set into a state with reduced current consumption. Entering Standby mode overrides the CMC bit, allowing the CAN transceiver to enter the low-power mode autonomously. The watchdog will, however, continue to monitor the microcontroller (Time-out mode) since it is powered via pin V1. In the event that the host microcontroller can provide a low-power mode with reduced current consumption in its Standby mode or Stop mode, the watchdog can be switched off entirely in Standby mode of the SBC. The SBC monitors the microcontroller supply current to ensure that there is no unobserved phase with disabled watchdog and running microcontroller. The watchdog will remain active until the supply current drops below IthL(V1). Below this current limit the watchdog is disabled. Should the current increase to IthH(V1), e.g. as result of a microcontroller wake-up from application specific hardware, the watchdog will start operating again with the previously used time-out period. If the watchdog is not triggered correctly, a system reset will occur and the SBC will enter Start-up mode. If Standby mode is entered from Normal mode with the selected watchdog OFF option, the watchdog will use the maximum time-out as defined for Standby mode until the supply current drops below the current detection threshold; the watchdog is now OFF. If the current increases again, the watchdog is immediately activated, again using the maximum watchdog time-out period. If the watchdog OFF option is selected during Standby mode, the last used watchdog period will define the time for the supply current to fall below the current detection threshold. This allows the user to align the current supervisor function to the application needs. Generally, the microcontroller can be activated from Standby mode via a system reset or via an interrupt without reset. This allows implementation of differentiated start-up behavior from Standby mode, depending on the application needs: * If the watchdog is still running during Standby mode, the watchdog can be used for cyclic wake-up behavior of the system. A dedicated Watchdog Time-out Interrupt Enable (WTIE) bit enables the microcontroller to decide whether to receive an interrupt or a hardware reset upon overflow. The interrupt option will be cleared in hardware automatically with each watchdog overflow to ensure that a failing main routine is detected while the interrupt service still operates. So the application software must set the interrupt behavior each time before a standby cycle is entered. * Any wake-up via the CAN-bus or the LIN-bus together with a local wake-up event will force a system reset event or an interrupt to the microcontroller. So it is possible to exit Standby mode without any system reset if required. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 10 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip When an interrupt event occurs the application software has to read the Interrupt register within tRSTN(INT). Otherwise a fail-safe system reset is forced and Start-up mode will be entered. If the application has read out the Interrupt register within the specified time, it can decide whether to switch into Normal mode via an SPI access or to stay in Standby mode. The following operations are possible from Standby mode: * Cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the microcontroller is triggered periodically and checked for the correct response) * Cyclic wake-up by the watchdog via a reset signal (a reset is performed periodically; the SBC provides information about the reset source to allow different start sequences after reset) * Wake-up by activity on the CAN-bus or LIN-bus via an interrupt signal to the microcontroller * Wake-up by bus activity on the CAN-bus or LIN-bus via a reset signal * Wake-up by increasing the microcontroller supply current without a reset signal (where a stable supply is needed for the microcontroller RAM contents to remain valid and wake-up from an external application not connected to the SBC) * Wake-up by increasing the microcontroller supply current with a reset signal * Wake-up due to a falling edge at pin WAKE forcing an interrupt to the microcontroller * Wake-up due to a falling edge at pin WAKE forcing a reset signal 6.2.6 Sleep mode In Sleep mode the microcontroller power supply (V1) and the INH/LIMP controlled external supplies are switched off entirely, resulting in minimum system power consumption. In this mode, the watchdog runs in Time-out mode or is completely off. Entering Sleep mode results in an immediate LOW level on pin RSTN, thus stopping any operation of the microcontroller. The INH/LIMP output is floating in parallel and pin V1 is disabled. Only pin SYSINH can remain active to support the V2 voltage supply; this depends on the V2C bit. It is also possible for V3 to be On, Off or in Cyclic mode to supply external wake-up switches. If the watchdog is not disabled in software, it will continue to run and force a system reset upon overflow of the programmed period time. The SBC enters Start-up mode and pin V1 becomes active again. This behavior can be used for a cyclic wake-up from Sleep mode. Depending on the application, the following operations can be selected from Sleep mode: * Cyclic wake-up by the watchdog (only in Time-out mode); a reset is performed periodically, the SBC provides information about the reset source to allow different start sequences after reset * Wake-up by activity on the CAN-bus, LIN-bus or falling edge at pin WAKE * An overload on V3, only if V3 is in a cyclic or in continuously on mode UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 11 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 6.2.7 Flash mode Flash mode can only be entered from Normal mode by entering a specific Flash mode entry sequence. This fail-safe control sequence comprises three consecutive write accesses to the Mode register, within the legal windows of the watchdog, using the operating mode codes 111, 001 and 111 respectively. As a result of this sequence, the SBC will enter Start-up mode and perform a system reset with the related reset source information (bits RSS = 0110). From Start-up mode the application software now has to enter Flash mode within tWD(init) by writing Operating Mode code 011 to the Mode register. This feeds back a successfully received hardware reset (handshake between the SBC and the microcontroller). The transition from Start-up mode to Flash mode is possible only once after completing the Flash entry sequence. The application can also decide not to enter Flash mode but to return to Normal mode by using the Operating Mode code 101 for handshaking. This erases the Flash mode entry sequence. The watchdog behavior in Flash mode is similar to its time-out behavior in Standby mode, but Operating Mode code 111 must be used for serving the watchdog. If this code is not used or if the watchdog overflows, the SBC immediately forces a reset and enters Start-up mode. Flash mode is properly exited using the Operating Mode code 110 (leave Flash mode), which results in a system reset with the corresponding reset source information. Other Mode register codes will cause a forced reset with reset source code `illegal Mode register code'. 6.3 On-chip oscillator The on-chip oscillator provides the clock signal for all digital functions and is the timing reference for the on-chip watchdog and the internal timers. If the on-chip oscillator frequency is too low or the oscillator is not running at all, there is an immediate transition to Fail-safe mode. The SBC will stay in Fail-safe mode until the oscillator has recovered to its normal frequency and the system receives a wake-up event. 6.4 Watchdog The watchdog provides the following timing functions: * Start-up mode; needed to give the software the opportunity to initialize the system * Window mode; detects too early and too late accesses in Normal mode * Time-out mode; detects a too late access, can also be used to restart or interrupt the microcontroller from time to time (cyclic wake-up function) * Off mode; fail-safe shut-down during operation thus preventing any blind spots in the system supervision The watchdog is clocked directly by the on-chip oscillator. To guarantee fail-safe control of the watchdog via the SPI, all watchdog accesses are coded with redundant bits. Therefore, only certain codes are allowed for a proper watchdog service. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 12 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip The following corrupted watchdog accesses result in an immediate system reset: * Illegal watchdog period coding; only ten different codes are valid * Illegal operating mode coding; only six different codes are valid Any microcontroller driven mode change is synchronized with a watchdog access by reading the mode information and the watchdog period information from the same register. This enables an easy software flow control with defined watchdog behavior when switching between different software modules. 6.4.1 Watchdog start-up behavior Following any reset event the watchdog is used to monitor the ECU start-up procedure. It observes the behavior of the RSTN pin for any clamping condition or interrupted reset wire. In case the watchdog is not properly served within tWD(init), another reset is forced and the monitoring procedure is restarted. In case the watchdog is again not properly served, the system enters Fail-safe mode (see also Figure 3, Start-up and Restart modes). 6.4.2 Watchdog window behavior Whenever the SBC enters Normal mode, the Window mode of the watchdog is activated. This ensures that the microcontroller operates within the required speed; a too fast as well as a too slow operation will be detected. Watchdog triggering using the Window mode is illustrated in Figure 4. period too early trigger restarts period trigger via SPI last trigger point 50 % trigger window 100 % earliest possible trigger point trigger restarts period (with different duration if desired) latest possible trigger point 50 % too early trigger window 100 % new period trigger via SPI earliest possible trigger point latest possible trigger point mce626 Fig 4. Watchdog triggering using Window mode UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 13 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip The SBC provides 10 different period timings, scalable with a 4-factor watchdog prescaler. The period can be changed within any valid trigger window. Whenever the watchdog is triggered within the window time, the timer will be reset to start a new period. The watchdog window is defined to be between 50 % and 100 % of the nominal programmed watchdog period. Any too early or too late watchdog access or wrong Mode register code access will result in an immediate system reset, entering Start-up mode. 6.4.3 Watchdog time-out behavior Whenever the SBC operates in Standby mode, in Sleep mode or in Flash mode, the active watchdog operates in Time-out mode. The watchdog has to be triggered within the actual programmed period time; see Figure 5. The Time-out mode can be used to provide cyclic wake-up events to the host microcontroller from Standby and Sleep modes. period trigger range time-out trigger via SPI earliest possible trigger point trigger restarts period (with different duration if desired) latest possible trigger point trigger range new period time-out mce627 Fig 5. Watchdog triggering using Time-out mode In Standby and in Flash mode the nominal periods can be changed with any SPI access to the Mode register. Any illegal watchdog trigger code results in an immediate system reset, entering Start-up mode. 6.4.4 Watchdog OFF behavior It is possible to switch the watchdog off completely In Standby and Sleep modes. For fail-safe reasons this is only possible if the microcontroller has stopped program execution. To ensure that there is no program execution, the V1 supply current is monitored by the SBC while the watchdog is switched off. When selecting the watchdog OFF code, the watchdog remains active until the microcontroller supply current has dropped below the current monitoring threshold IthL(V1). After the supply current has dropped below the threshold, the watchdog stops at the end of the watchdog period. In case the supply current does not drop below the monitoring threshold, the watchdog stays active. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 14 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip If the microcontroller supply current increases above IthH(V1) while the watchdog is OFF, the watchdog is restarted with the last used watchdog period time and a watchdog restart interrupt is forced, if enabled. In case of a direct mode change towards Standby mode with watchdog OFF selected, the longest possible watchdog period is used. It should be noted that in Sleep mode V1 current monitoring is not active. 6.5 System reset The reset function of the UJA1061 offers two signals to deal with reset events: * RSTN; the global ECU system reset * EN; a fail-safe global enable signal 6.5.1 RSTN pin The system reset pin (RSTN) is a bidirectional input / output. Pin RSTN is active LOW with selectable pulse length upon the following events; see Figure 3: * Power-on (first battery connection) or VBAT42 below power-on reset threshold voltage * Low V1 supply * V1 current above threshold during Standby mode while watchdog OFF behavior is selected * * * * * * * * * V3 is down due to short-circuit condition during Sleep mode RSTN externally forced LOW, falling edge event Successful preparation for Flash mode completed Successful exit from Flash mode Wake-up from Standby mode via pins CAN, LIN or WAKE if programmed accordingly, or any wake-up event from Sleep mode Wake-up event from Fail-safe mode Watchdog trigger failures (too early, overflow, wrong code) Illegal mode code via SPI applied Interrupt not served within tRSTN(INT) All of these reset events have a dedicated reset source in the System Status register to allow distinction between the different events. The SBC will lengthen any reset event to 1 ms or 20 ms to ensure that external hardware is properly reset. After the first battery connection, a short power-on reset of 1 ms is provided after voltage V1 is present. Once started, the microcontroller can set the Reset Length Control (RLC) bit within the System Configuration register; this allows the reset pulse to be adjusted for future reset events. With this bit set, all reset events are lengthened to 20 ms. Due to fail-safe behavior, this bit will be set automatically (to 20 ms) in Restart mode or Fail-safe mode. With this mechanism it is guaranteed that an erroneously shortened reset pulse will restart any microcontroller, at least within the second trial by using the long reset pulse. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 15 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip The behavior of pin RSTN is illustrated in Figure 6. The duration of tRSTNL depends on the setting of the RLC bit (defines the reset length). Once an external reset event is detected the system controller enters the Start-up mode. The watchdog now starts to monitor pin RSTN as illustrated in Figure 7. If the RSTN pin is not released in time then Fail-safe mode is entered as shown in Figure 3. V1 Vrel(UV)(V1) Vdet(UV)(V1) time power-up VRSTN undervoltage missing watchdog access undervoltage spike powerdown time tRSTNL tRSTNL tRSTNL coa054 Fig 6. Reset pin behavior VRSTN time t RSTNL RSTN externally forced LOW t WD(init) VRSTN time t RSTNL RSTN externally forced LOW t WD(init) 001aad181 Fig 7. Reset timing diagram UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 16 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Pin RSTN is monitored for a continuously clamped LOW situation. Once the SBC pulls pin RSTN HIGH but pin RSTN level remains LOW for longer than tRSTN(CLT), the SBC immediately enters Fail-safe mode since this indicates an application failure. The SBC also detects if pin RSTN is clamped HIGH. If the HIGH-level remains on the pin for longer than tRSTN(CHT) while pin RSTN is driven internally to a LOW-level by the SBC, the SBC falls back immediately to Fail-safe mode since the microcontroller cannot be reset any more. By entering Fail-safe mode, the V1 voltage regulator shuts down and the microcontroller stops. Additionally, chattering reset signals are handled by the SBC in such a way that the system safely falls back to Fail-safe mode with the lowest possible power consumption. 6.5.2 EN output Pin EN can be used to control external hardware such as power components or as a general purpose output if the system is running properly. During all reset events, when pin RSTN is pulled LOW, the EN control bit will be cleared, pin EN will be pulled LOW and will stay LOW after pin RSTN is released. In Normal mode and Flash mode of the SBC, the microcontroller can set the EN control bit via the SPI. This results in releasing pin EN which then returns to a HIGH-level. 6.6 Power supplies 6.6.1 BAT14, BAT42 and SYSINH The SBC has two supply pins, pin BAT42 and pin BAT14. Pin BAT42 supplies most of the SBC where pin BAT14 only supplies the linear voltage regulators and the INH/LIMP output pin. This supply architecture allows different supply strategies including the use of external DC-to-DC converters controlled by the pin SYSINH. 6.6.1.1 SYSINH output The SYSINH output is a high-side switch from BAT42. It is activated whenever the SBC requires supply voltage to pin BAT14, e.g. when V1 or V2 is on (see Figure 3 and Figure 8). Otherwise pin SYSINH is floating. Pin SYSINH can be used to control e.g. an external step-down voltage regulator to pin BAT14, to reduce power consumption in low-power modes. 6.6.2 Voltage regulators V1 and V2 The UJA1061 has two independent voltage regulators supplied out of the BAT14 pin. Regulator V1 is intended to supply the microcontroller. Regulator V2 is reserved for the CAN transceiver. 6.6.2.1 Voltage regulator V1 The V1 voltage is continuously monitored to provide the system reset signal when undervoltage situations occur. Whenever the V1 voltage falls below one of the three programmable thresholds, a hardware reset is forced. A dedicated V1 supply comparator (V1 Monitor) observes V1 for undervoltage events lower than VUV(VFI). This allows the application to receive a supply warning interrupt in case one of the lower V1 undervoltage reset thresholds is selected. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 17 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip The V1 regulator is overload protected. The maximum output current available from pin V1 depends on the voltage applied at pin BAT14 (see Table 26). For thermal reasons, the total power dissipation should be taken into account. 6.6.2.2 Voltage regulator V2 Voltage regulator V2 provides a 5 V supply for the CAN transmitter. The pin V2 is intended for the connection of external buffering capacitors. V2 is controlled autonomously by the CAN transceiver control system and is activated on any detected CAN-bus activity, or if the CAN transceiver is enabled by the application microcontroller. V2 is short-circuit protected and will be disabled in case of an overload situation. Dedicated bits in the System Diagnosis register and the Interrupt register provide V2 status feedback to the application. Besides the autonomous control of V2 there is a software accessible bit which allows activation of V2 manually (V2C). This allows V2 to be used for other application purposes when CAN is not actively used (e.g. while CAN is off-line). Generally, V2 should not be used for other application hardware while CAN is in use. If the regulator V2 is not able to start within the V2 clamped LOW time (> tV2(CLT)), or if a short-circuit has been detected during an already activated V2, then V2 is disabled and the V2D bit in the System Diagnosis register is cleared. Additionally the CTC bit in the Physical Layer Control register is set and the V2C bit is cleared. Reactivation of voltage regulator V2 can be done by: * * * * Clearing the CTC bit while CAN is in Active mode Wake-up via CAN while CAN is not in Active mode Setting the V2C bit When entering CAN Active mode 6.6.3 Switched battery output V3 V3 is a high-side switched BAT42-related output which is used to drive external loads such as wake-up switches or relays. The features of V3 are as follows: * Three application-controlled operating modes; On, Off and Cyclic. * Two different cyclic modes allow the supply of external wake-up switches; these switches are powered intermittently, thus reducing the system's power consumption in case a switch is continuously active; the wake-up input of the SBC is synchronized with the V3 cycle time. * The switch is protected against current overloads. If V3 is overloaded, pin V3 is automatically disabled. The corresponding System Diagnosis register bit is reset and an interrupt is forced (if enabled). During Sleep mode, a wake-up is forced and the corresponding reset source code becomes available in the RSS bits of the System Status register. This signals that the wake-up source via V3 supplied wake-up switches has been lost. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 18 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 6.7 CAN transceiver The integrated fault-tolerant CAN transceiver of the UJA1061 is an advanced ISO11898-3 compliant transceiver and is interoperable with the TJA1054 and TJA1054A stand-alone transceivers. In addition to standard fault-tolerant CAN transceivers the UJA1061 transceiver provides the following features: * Enhanced error handling and reporting of bus and RXD/TXD failures; these failures are separately identified in the System Diagnosis register * Integrated autonomous control system for determining the mode of the CAN transceiver * Ground shift detection with two selectable warning levels, to detect possible local ground problems before the CAN communication is affected * On-line Listen mode with global wake-up message filter allows partial networking * Bus connections are truly floating when power is off 6.7.1 Mode control The controller of the CAN transceiver provides four modes of operation: Active mode, On-line mode, On-line Listen mode and Off-line mode; see Figure 8. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 19 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Active mode V2 : ON/OFF (V2D) transmitter: ON/OFF (CTC) RXDC: bit stream/HIGH (V2D) CANL bias V2/floating/(V2D) CPNC = 0 or 1 SBS enters Normal or Flash mode AND CMC = 1 CMC = 0 AND CPNC = 0 CMC = 0 AND CPNC = 1 CMC = 1 On-line mode V2 : ON/OFF (V2D) transmitter: OFF RXDC: wake-up (active LOW) CANL bias V2/floating/(V2D) CPNC = 0 CPNC = 1 On-line Listen mode V2 : ON/OFF (V2D) transmitter: OFF RXDC: V1 CANL bias V2/floating/(V2D) CPCN = 1 CMC = 1 global wake-up message detected OR CPNC = 0 no activity for t > t off-line CAN wake-up filter passed AND CPNC = 1 CAN wake-up filter passed AND CPNC = 0 no activity for t > t off-line Off-line mode V2 : ON/OFF (V2C/V2D) transmitter: OFF RXDC: V1 CANL bias BAT42/floating/(V2D) CPCN = 0 or 1 power-on 001aaf003 Fig 8. States of the CAN transceiver In the System Diagnosis register two dedicated CAN status bits (CANMD) are available to signal the mode of the transceiver. 6.7.1.1 Active mode In Active mode the CAN transceiver can transmit data to and receive data from the CAN bus. To enter Active mode the CMC bit must be set in the Physical Layer Control register and the SBC must be in Normal mode or Flash mode. In Active mode voltage regulator V2 is activated automatically. The CTC bit can be used to set the CAN transceiver to a Listen-only mode. The transmitter output stage is disabled in this mode. After an overload condition on voltage regulator V2, the CTC bit must be cleared for reactivating the CAN transmitter. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 20 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip When leaving Active mode the CAN transmitter is disabled and the CAN receiver is monitoring the CAN-bus for a valid wake-up. The CAN termination is then working autonomously. 6.7.1.2 On-line mode In On-line mode the CAN bus pins and RTL and RTH pins are biased to the normal levels. The CAN transmitter is deactivated and RXDC reflects the CAN wake-up status. A CAN wake-up event is signalled to the microcontroller by setting pin RXDC to LOW. If the bus stays continuously dominant or recessive for the Off-line time (toff-line), the Off-line state will be entered. 6.7.1.3 On-line Listen mode On-line Listen mode behaves similar to On-line mode, but all activity on the CAN-bus, with exception of a special global wake-up request, is ignored. The global wake-up request is described in Section 6.7.2. Pin RXDC is kept HIGH. 6.7.1.4 Off-line mode Off-line mode is the low-power mode of the CAN transceiver. The CAN transceiver is disabled to save supply current and is high-ohmic terminated to ground. The CAN off-line time is programmable in two steps with the CAN Off-line Timer Control (COTC) bit. When entering On-line (Listen) mode from Off-line mode the CAN off-line time is temporarily extended to toff-line(ext). 6.7.2 CAN wake-up To wake-up the UJA1061 via CAN it has to be distinguished between a conventional wake-up and a global wake-up in case partial networking is enabled (bit CPNC = 1). To pass the wake-up filter for a conventional wake-up a dominant, recessive, dominant signal on the CAN-bus is needed. For a global wake-up out of On-line Listen mode two distinct CAN data patterns are required (shown in hexadecimal code here): * In the Initial message: C6EE EEEE EEEE EEEF * In the Global wake-up message: C6EE EEEE EEEE EE37 The second pattern must be received within ttimeout after receiving the first pattern. Any CAN-ID can be used with these data patterns. If the CAN transceiver enters On-line Listen mode directly from Off-line mode the global wake-up message is sufficient to wake-up the SBC. This pattern must be received within ttimeout after entering On-line Listen mode. Should ttimeout elapse before receiving the global wake-up message, then both messages are required for a CAN wake-up. 6.7.3 Termination control In Active mode, On-line mode and On-line Listen mode, CANH is terminated to GND and CANL is terminated to pin V2 via the external termination resistors applied to RTH and RTL. In case of detected bus failures, the termination changes according to the ISO 11898-3 standard. In Off-line mode pin CANH stays terminated to GND but with a diode in UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 21 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip between (reverse supply protection) while pin CANL becomes terminated to pin BAT42 (via pin RTH and pin RTL). If pin V2 is disabled due to an overload condition RTH and RTL become floating. 6.7.4 Bus, RXD and TXD failure detection The UJA1061 can distinguish between bus, RXD and TXD failures as indicated in Table 3. All failures are signalled separately in the CANFD bits in the System Diagnosis register. Any change (detection and recovery) forces an interrupt to the microcontroller, if this interrupt is enabled. Table 3. Failure HxVCC HxBAT HxGND LxBAT LxGND LxVCC HxL H// L// Bus Dom CAN-bus, RXD and TXD failure detection Description CANH to VCC (5 V) short-circuit CANH to BAT (14 V and 42 V) short-circuit CANH to GND short-circuit CANL to BAT (14 V and 42 V) short-circuit CANL to GND short-circuit CANL to VCC (5 V) short-circuit CANH to CANL short-circuit CANH interrupted CANL interrupted bus is continuously clamped dominant (double failure); even within Single-wire mode the receiver remains dominant Driver and biasing circuit disabling CANH off, weak RTH CANH off, weak RTH none CANL off, weak RTL[1] CANL off, weak RTL none CANL off, weak RTL none none CANL off, weak RTL Bus Rec bus is continuously clamped recessive none (double failure); driving messages to the bus is not possible even while the driver is active pin TXDC is continuously clamped dominant (handles also RXDC to TXDC short-circuits) transmitter disabled but no change in biasing TxDC Dom RxDC Rec RxDC Dom [1] pin RXDC is continuously clamped recessive transmitter disabled but no change in biasing pin RXDC is continuously clamped dominant none CANL stays active with weak short-circuits to BAT due to wake-up requirements within large networks. 6.7.4.1 TXDC dominant clamping If the TXDC pin is clamped dominant for longer than tTXDC(dom) the CAN transmitter is disabled. After the TXDC pin becomes recessive the transmitter is reactivated automatically when detecting bus activity or manually by setting and clearing the CTC bit. 6.7.4.2 RXDC recessive clamping If the RXDC pin is clamped recessive while the CAN bus is dominant the CAN transmitter is disabled. The transmitter is reactivated automatically when RXDC becomes dominant or manually by setting and clearing the CTC bit. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 22 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 6.7.4.3 GND shift detection The SBC can detect ground shifts in reference to the CAN bus. Two different ground shift detection levels can be selected with the GSTHC bit in the System Configuration register. The failure can be read out in the System Diagnosis register. Any detected or recovered GND shift event is signalled with an interrupt, if enabled. 6.8 LIN transceiver The integrated LIN transceiver of the UJA1061 is a LIN 2.0 compliant transceiver. The transceiver has the following features: * SAE J2602 compliant and compatible with LIN revision 1.3 * Fail-safe LIN termination to BAT42 via dedicated RTLIN pin * Enhanced error handling and reporting of bus and TXD failures; these failures are separately identified in the System Diagnosis register 6.8.1 Mode control Active mode transmitter: ON/OFF (LTC) receiver: ON RXDL: bitstream RTLIN: ON/75 A SBC enters Normal or Flash mode AND LMC = 1 SBC enters Stand-by, Start-up, Restart or Fail-safe mode OR LMC = 0 Off-line mode power-on transmitter: OFF receiver: wake-up RXDL: wake-up status RTLIN: 75 A/OFF SBC enters Fail-safe mode 001aad184 Fig 9. States LIN transceiver The controller of the LIN transceiver provides two modes of operation: Active mode and Off-line mode; see Figure 9. In Off-line mode the transmitter and receiver do not consume current, but wake-up events will be recognized by the separate wake-up receiver. 6.8.1.1 Active mode In Active mode the LIN transceiver can transmit data to and receive data from the LIN bus. To enter Active mode the LMC bit must be set in the Physical Layer Control register and the SBC must be in Normal mode or Flash mode. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 23 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip The LTC bit can be used to set the LIN transceiver to a Listen-only mode. The transmitter output stage is disabled in this mode. When leaving Active mode the LIN transmitter is disabled and the LIN receiver is monitoring the LIN-bus for a valid wake-up. 6.8.1.2 Off-line mode Off-line mode is the low power mode of the LIN transceiver. The LIN transceiver is disabled to save supply current. Pin RXDL reflects any wake-up event at the LIN-bus. 6.8.2 LIN wake-up For a remote wake-up via LIN a LIN-bus signal is required as shown in Figure 10. LIN wake-up tBUS(LIN) 001aad447 Fig 10. LIN wake-up timing diagram 6.8.3 Termination control The RTLIN pin is in one of 3 different states: RTLIN = on, RTLIN = off or RTLIN = 75 A; see Figure 11. During Active mode, with no short-circuit between the LIN-bus and GND, pin RTLIN provides an internal switch to BAT42. For master and slave operation an external resistor, 1 k or 30 k respectively, can be applied between pins RTLIN and LIN. An external diode in series with the termination resistor is not required due to the incorporated internal diode. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 24 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Active mode and receiver dominant > t LIN(dom)(det) OR Off-line mode RTLIN = ON supplied directly out of BAT42 RTLIN = 75 A supplied directly out of BAT42 Active mode and receiver recessive > t LIN(dom)(rec) OR mode change to Active mode Off-line mode AND receiver recessive > t LIN(dom)(rec) mode change to Active mode Off-line mode AND receiver dominant > t LIN(dom)(det) power-on RTLIN = OFF 001aad183 Fig 11. States of the RTLIN pin 6.8.4 LIN slope control The LSC bit in the Physical Layer Control register offers a choice between two LIN slope times, allowing communication up to 20 kbit/s (normal) or up to 10.4 kbit/s (low slope). 6.8.5 LIN driver capability Setting the LDC bit in the Physical Layer Control register will increase the driver capability of the LIN output stage. This feature is used in auto-addressing systems, where the standard LIN 2.0 drive capability is insufficient. 6.8.6 Bus and TXDL failure detection The SBC handles and reports the following LIN-bus related failures: * LIN-bus shorted to ground * LIN-bus shorted to VBAT14 or VBAT42; the transmitter is disabled * TXDL clamped dominant; the transmitter is disabled These failure events force an interrupt to the microcontroller whenever the status changes and the corresponding interrupt is enabled. 6.8.6.1 TXDL dominant clamping If the TXDL pin is clamped dominant for longer than tTXDL(dom)(dis) the LIN transmitter is disabled. After the TXDL pin becomes recessive the transmitter is reactivated automatically when detecting bus activity or manually by setting and clearing the LTC bit. 6.8.6.2 LIN dominant clamping When the LIN-bus is clamped dominant for longer than tLIN(dom)(det) (which is longer than tTXDL(dom)(dis)), the state of the LIN termination is changed according to Figure 11. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 25 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 6.8.6.3 LIN recessive clamping If the LIN bus pin is clamped recessive while TXDL is driven dominant the LIN transmitter is disabled. The transmitter is reactivated automatically when the LIN bus becomes dominant or manually by setting and clearing the LTC bit. 6.9 Inhibit and limp-home output The INH/LIMP output pin is a 3-state output pin which can be used either as an inhibit for an extra (external) voltage regulator, or as a `limp-home' output. The pin is controlled via the ILEN bit and ILC bit in the System Configuration register; see Figure 12. When pin INH/LIMP is used as inhibit output, a pull-down resistor to GND ensures a default LOW level. The pin can be set to HIGH according to the state diagram. When pin INH/LIMP is used as limp-home output, a pull-up resistor to VBAT42 ensures a default HIGH level. The pin is automatically set to LOW when the SBC enters Fail-safe mode. state change via SPI OR enter Fail-safe mode INH/LIMP: HIGH ILEN = 1 ILC = 1 state change via SPI state change via SPI OR (enter Start-up mode after wake-up reset, external reset or V1 undervoltage) OR enter Restart mode OR enter Sleep mode state change via SPI INH/LIMP: LOW ILEN = 1 ILC = 0 state change via SPI OR enter Fail-safe mode state change via SPI INH/LIMP: floating power-on ILEN = 0 ILC = 1/0 001aad178 Fig 12. States of the INH/LIMP pin 6.10 Wake-up input The WAKE input comparator is triggered by negative edges on pin WAKE. Pin WAKE has an internal pull-up resistor to BAT42. It can be operated in two sampling modes which are selected via the WAKE Sample Control bit (WSC): * Continuous sampling (with an internal clock) if the bit is set * Sampling synchronized to the cyclic behavior of V3 if the bit is cleared; see Figure 13. This is to save bias current within the external switches in low-power operation. Two repetition times are possible, 16 ms and 32 ms. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 26 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip If V3 is continuously ON, the WAKE input will be sampled continuously, regardless of the level of bit WSC. The dedicated bits Edge Wake-up Status (EWS) and WAKE Level Status (WLS) in the System Status register reflect the actual status of pin WAKE. The WAKE port can be disabled by clearing the WEN bit in the System Configuration register. tw(CS) ton(CS) V3 approximately 70 % tsu(CS) sample active VWAKE signal already HIGH due to biasing (history) button pushed button released signal remains LOW due to biasing (history) flip flop VINTN 001aac307 Fig 13. Pin WAKE, cyclic sampling via V3 6.11 Interrupt output Pin INTN is an open-drain interrupt output. It is forced LOW whenever at least one bit in the Interrupt register is set. By reading the Interrupt register all bits are cleared. The Interrupt register will also be cleared during a system reset (RSTN LOW). As the microcontroller operates typically with an edge-sensitive interrupt port, pin INTN will be HIGH for at least tINTN after each read-out of the Interrupt register. Without further interrupts within tINTN pin INTN stays HIGH, otherwise it will revert to LOW again. To prevent the microcontroller from being slowed down by repetitive interrupts, in Normal mode some interrupts are only allowed to occur once per watchdog period; see Section 6.13.7. If an interrupt is not read out within tRSTN(INT) a system reset is performed. 6.12 Temperature protection The temperature of the SBC chip is monitored as long as the microcontroller voltage regulator V1 is active. To avoid an unexpected shutdown of the application by the SBC, the temperature protection will not switch-off any part of the SBC or activate a defined system stop of its own accord. If the temperature is too high it generates an interrupt to the microcontroller (C), if enabled, and the corresponding status bit will be set. The microcontroller can then decide whether to switch-off parts of the SBC to decrease the chip temperature. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 27 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 6.13 SPI interface The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller, supporting multi-slave and multi-master operation. The SPI is configured for full duplex data transfer, so status information is returned when new control data is shifted in. The interface also offers a read-only access option, allowing registers to be read back by the application without changing the register content. The SPI uses four interface signals for synchronization and data transfer: * * * * SCS - SPI chip select; active LOW SCK - SPI clock; default level is LOW due to low-power concept SDI - SPI data input SDO - SPI data output; floating when pin SCS is HIGH Bit sampling is performed on the falling clock edge and data is shifted on the rising clock edge; see Figure 14. SCS SCK 01 sampled 02 03 04 15 16 SDI X MSB 14 13 12 01 LSB X SDO floating X MSB 14 13 12 01 LSB floating mce634 Fig 14. SPI timing protocol To protect against wrong or illegal SPI instructions, the SBC detects the following SPI failures: * SPI clock count failure (wrong number of clock cycles during one SPI access): only 16 clock periods are allowed within one SCS cycle. Any deviation from the 16 clock cycles results in an SPI failure interrupt, if enabled. The access is ignored by the SBC. In Start-up and Restart mode a reset is forced instead of an interrupt * Forbidden mode changes according to Figure 3 result in an immediate system reset * Illegal Mode register code. Undefined operating mode or watchdog period coding results in an immediate system reset; see Section 6.13.3 6.13.1 SPI register mapping Any control bit which can be set by software is readable by the application. This allows software debugging as well as control algorithms to be implemented. Watchdog serving and mode setting is performed within the same access cycle; this only allows an SBC mode change whilst serving the watchdog. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 28 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Each register carries 12 data bits; the other 4 bits are used for register selection and read/write definition. 6.13.2 Register overview The SPI interface gives access to all SBC registers; see Table 4. The first two bits (A1 and A0) of the message header define the register address, the third bit is the read register select bit (RRS) to select one out of two possible feedback registers; the fourth bit (RO) allows `read only' access to one of the feedback registers. Which of the SBC registers can be accessed also depends on the SBC operating mode. Table 4. Register overview Operating mode all modes Normal mode; Standby mode; Flash mode Start-up mode; Restart mode 10 Normal mode; Standby mode Start-up mode; Restart mode; Flash mode 11 Normal mode; Standby mode Start-up mode; Restart mode; Flash mode Write access (RO = 0) Read access (RO = 0 or RO = 1) Read Register Select (RRS) bit = 0 Mode register Interrupt Enable register System Status register Interrupt Enable Feedback register Interrupt Enable Feedback register System Configuration Feedback register System Configuration Feedback register Physical Layer Control Feedback register Physical Layer Control Feedback register Read Register Select (RRS) bit = 1 System Diagnosis register Interrupt register Register address bits (A1, A0) 00 01 Special Mode register System Configuration register General Purpose register 0 Special Mode Feedback register General Purpose Feedback register 0 General Purpose Feedback register 0 General Purpose Feedback register 1 General Purpose Feedback register 1 Physical Layer Control register General Purpose register 1 6.13.3 Mode register In the Mode register the watchdog is defined and re-triggered, and the SBC operating mode is selected. The Mode register also contains the global enable output bit (EN) and the Software Development Mode (SDM) control bit. During system operation cyclic access to the Mode register is required to serve the watchdog. This register can be written to in all modes. At system start-up the Mode register must be written to within tWD(init) from releasing RSTN (HIGH-level on pin RSTN). Any write access is checked for proper watchdog and system mode coding. If an illegal code is detected, access is ignored by the SBC and a system reset is forced in accordance with the state diagram of the system controller; see Figure 3. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 29 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 5. Bit 15 and 14 13 12 11 to 6 5 to 3 Mode register bit description (bits 15 to 12 and 5 to 0) Symbol A1, A0 RRS RO NWP[5:0] OM[2:0] Description register address Read Register Select Read Only see Table 6 Operating Mode 001 010 011 100 101 110 111 Normal mode Standby mode initialize Flash mode[1] Sleep mode initialize Normal mode leave Flash mode Flash mode[1] Software Development mode enabled[2] normal watchdog, interrupt, reset monitoring and fail-safe behavior EN output pin HIGH EN output pin LOW reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit Value 00 1 0 1 0 Function select Mode register read System Diagnosis register read System Status register read selected register without writing to Mode register read selected register and write to Mode register 2 SDM Software Development Mode Enable reserved 1 0 1 0 0 1 0 EN - [1] Flash mode can be entered only with the watchdog service sequence `Normal mode to Flash mode to Normal mode to Flash mode', while observing the watchdog trigger rules. With the last command of this sequence the SBC forces a system reset, and enters Start-up mode to prepare the microcontroller for flash memory download. The four RSS bits in the System Status register reflect the reset source information, confirming the Flash entry sequence. By using the Initializing Flash mode (within tWD(init) after system reset) the SBC will now successfully enter Flash mode. See Section 6.14.1. [2] Table 6. Bit Mode register bit description (bits 11 to 6)[1] Symbol Description Value Time Normal mode (ms) Standby mode (ms) 20 40 80 160 320 640 1024 2048 4096 OFF[2] Flash mode (ms) 20 40 80 160 320 640 1024 2048 4096 8192 Sleep mode (ms) 160 320 640 1024 2048 3072 4096 6144 8192 OFF[3] 11 to 6 NWP[5:0] Nominal 00 1001 Watchdog Period 00 1100 WDPRE = 00 (as 01 0010 set in the Special 01 0100 Mode register) 01 1011 10 0100 10 1101 11 0011 11 0101 11 0110 4 8 16 32 40 48 56 64 72 80 UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 30 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 6. Bit Mode register bit description (bits 11 to 6)[1] ...continued Symbol Description Value Time Normal mode (ms) Standby mode (ms) 30 60 120 240 480 960 1536 3072 6144 OFF[2] 50 100 200 400 800 1600 1560 5120 10240 OFF[2] 70 140 280 560 1120 2240 3584 7168 14336 OFF[2] Flash mode (ms) 30 60 120 240 480 960 1536 3072 6144 12288 50 100 200 400 800 1600 1560 5120 10240 20480 70 140 280 560 1120 2240 3584 7168 14336 28672 Sleep mode (ms) 240 480 960 1536 3072 4608 6144 9216 12288 OFF[3] 400 800 1600 2560 5120 7680 10240 15360 20480 OFF[3] 560 1120 2240 3584 7168 10752 14336 21504 28672 OFF[3] 11 to 6 NWP[5:0] Nominal 00 1001 Watchdog Period 00 1100 WDPRE = 01 (as 01 0010 set in the Special 01 0100 Mode register) 01 1011 10 0100 10 1101 11 0011 11 0101 11 0110 Nominal 00 1001 Watchdog Period 00 1100 WDPRE = 10 (as 01 0010 set in the Special 01 0100 Mode register) 01 1011 10 0100 10 1101 11 0011 11 0101 11 0110 Nominal 001001 Watchdog Period 001100 WDPRE = 11 (as 010010 set in the Special 010100 Mode register) 011011 100100 101101 110011 110101 110110 6 12 24 48 60 72 84 96 108 120 10 20 40 80 100 120 140 160 180 200 14 28 56 112 140 168 196 224 252 280 [1] [2] [3] The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for fosc = 512 kHz. See Section 6.4.4. The watchdog is immediately disabled on entering Sleep mode, with watchdog OFF behavior selected, because pin RSTN is immediately pulled LOW by the mode change. V1 is switched off after pulling pin RSTN LOW to guarantee a safe Sleep mode entry without dips on V1; see Section 6.4.4. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 31 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 6.13.4 System Status register This register allows status information to be read back from the SBC. This register can be read in all modes. Table 7. Bit 15 and 14 13 12 System Status register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 00 0 1 0 11 to 8 RSS[3:0] Reset Source[1] 0000 read System Status register without writing to Mode register read System Status register and write to Mode register power-on reset; first connection of BAT42 or BAT42 below power-on voltage threshold or RSTN was forced LOW externally cyclic wake-up out of Sleep mode low V1 supply; V1 has dropped below the selected reset threshold V1 current above threshold within Standby mode while watchdog OFF behavior and reset option (V1CMC bit) are selected V3 voltage is down due to overload occurring during Sleep mode SBC successfully left Flash mode SBC ready to enter Flash mode CAN wake-up event LIN wake-up event local wake-up event (via pin WAKE) wake-up out of Fail-safe mode watchdog overflow watchdog not initialized in time; tWD(init) exceeded watchdog triggered too early; window missed illegal SPI access interrupt not served within tRSTN(INT) CAN wake-up detected; cleared upon read no CAN wake-up LIN wake-up detected; cleared upon read no LIN wake-up pin WAKE negative edge detected; cleared upon read pin WAKE no edge detected pin WAKE above threshold pin WAKE below threshold chip temperature exceeds the warning limit chip temperature is below the warning limit Software Development mode on Software Development mode off (c) NXP B.V. 2010. All rights reserved. Function read System Status register 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 7 6 5 4 3 2 CWS LWS EWS WLS TWS SDMS CAN Wake-up Status LIN Wake-up Status Edge Wake-up Status WAKE Level Status Temperature Warning Status Software Development Mode Status 1 0 1 0 1 0 1 0 1 0 1 0 UJA1061_6 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 06 -- 9 March 2010 32 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 7. Bit 1 0 System Status register bit description ...continued Symbol ENS PWONS Description Enable status Power-on reset Status Value 1 0 1 0 Function pin EN output activated (V1-related HIGH level) pin EN output released (LOW level) power-on reset; cleared after a successfully entered Normal mode no power-on reset [1] The RSS bits are updated with each reset event and not cleared. The last reset event is captured. 6.13.5 System Diagnosis register This register allows diagnosis information to be read back from the SBC. This register can be read in all modes. Table 8. Bit 15 and 14 13 12 System Diagnosis register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 00 1 1 0 11 10 to 7 GSD CANFD [3:0] Ground Shift Diagnosis CAN failure diagnosis 1 0 1111 1110 1100 1101 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 6 and 5 LINFD[1:0] LIN failure diagnosis 11 10 01 00 4 V3D V3 diagnosis 1 0 UJA1061_6 Function read System Diagnosis register read System Diagnosis register without writing to Mode register read System Diagnosis register and write to Mode register system GND shift is outside selected threshold system GND shift is within selected threshold TXDC is clamped dominant RXDC is clamped dominant BUS is clamped dominant (dual failure situation) RXDC is clamped recessive BUS is clamped recessive (dual failure situation) reserved CANH is shorted to CANL (failure case 7) CANL is shorted to VCC (failure case 6a) CANL is shorted to VBAT (failure case 6) CANH is shorted to GND (failure case 5) CANL is shorted to GND (failure case 4) CANH is shorted to VCC (failure case 3a) CANH is shorted to VBAT (failure case 3) CANL wire is interrupted (failure case 2) CANH wire is interrupted (failure case 1) no failure TXDL is clamped dominant LIN is shorted to GND (dominant clamped) LIN is shorted to VBAT (recessive clamped) no failure OK fail; V3 is disabled due to an overload situation (c) NXP B.V. 2010. All rights reserved. All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 06 -- 9 March 2010 33 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 8. Bit 3 2 System Diagnosis register bit description ...continued Symbol V2D V1D Description V2 diagnosis V1 diagnosis Value 1 0 1 0 Function OK[1] fail; V2 is disabled due to an overload situation OK; V1 always above VUV(VFI) since last read access fail; V1 was below VUV(VFI) since last read access; bit is set again with read access CAN is in Active mode CAN is in On-line mode CAN is in On-line Listen mode CAN is in Off-line mode, or V2 is not active 1 and 0 CANMD [1:0] CAN Mode Diagnosis 11 10 01 00 [1] V2D will be set when V2 is reactivated after a failure. See Section 6.6.2.2. 6.13.6 Interrupt Enable register and Interrupt Enable Feedback register These registers allow setting, clearing and reading back the interrupt enable bits of the SBC. Table 9. Bit 15 and 14 13 12 Interrupt Enable register and Interrupt Enable Feedback register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 01 1 0 1 0 11 WTIE Watchdog Time-out Interrupt Enable[1] 1 Function select the Interrupt Enable register read the Interrupt register read the Interrupt Enable Feedback register read the register selected by RRS without writing to Interrupt Enable register read the register selected by RRS and write to Interrupt Enable register a watchdog overflow during Standby causes an interrupt instead of a reset event (interrupt based cyclic wake-up feature) no interrupt forced on watchdog overflow; a reset is forced instead exceeding or dropping below the temperature warning limit causes an interrupt no interrupt forced exceeding or dropping below the GND shift limit causes an interrupt no interrupt forced wrong number of CLK cycles (more than, or less than 16) forces an interrupt; from Start-up mode and Restart mode a reset is performed instead of an interrupt no interrupt forced; SPI access is ignored if the number of cycles does not equal 16 should always be set to logic 0 clearing of V1D, V2D or V3D forces an interrupt no interrupt forced 0 10 OTIE Over-Temperature Interrupt Enable Ground Shift Interrupt Enable SPI clock count Failure Interrupt Enable 1 0 9 GSIE 1 0 8 SPIFIE 1 0 7 6 VFIE reserved 0 Voltage Failure Interrupt 1 Enable 0 UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 34 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 9. Bit 5 Interrupt Enable register and Interrupt Enable Feedback register bit description ...continued Symbol CANFIE Description CAN Failure Interrupt Enable LIN Failure Interrupt Enable WAKE Interrupt Enable[2] Value 1 0 Function any change of the CAN Failure status bits forces an interrupt no interrupt forced any change of the LIN Failure status bits forces an interrupt no interrupt forced a negative edge at pin WAKE generates an interrupt in Normal mode, Flash mode or Standby mode a negative edge at pin WAKE generates a reset in Standby mode; No interrupt in any other mode a watchdog restart during watchdog OFF generates an interrupt no interrupt forced CAN-bus event results in a wake-up interrupt in Standby mode and in Normal or Flash mode (unless CAN is in Active mode already) CAN-bus event results in a reset in Standby mode; No interrupt in any other mode LIN-bus event results in a wake-up interrupt in Standby mode and in Normal or Flash mode (unless LIN is in Active mode already) LIN-bus event results in a reset in Standby mode; no interrupt in any other mode 4 3 LINFIE WIE 1 0 1 0 2 WDRIE Watchdog Restart Interrupt Enable CAN Interrupt Enable 1 0 1 CANIE 1 0 0 LINIE LIN Interrupt Enable 1 0 [1] [2] This bit is cleared automatically upon each overflow event. It has to be set in software each time the interrupt behavior is required (fail-safe behavior). WEN (in the System Configuration register) has to be set to activate the WAKE port function globally. 6.13.7 Interrupt register The Interrupt register allows the cause of an interrupt event to be read. The register is cleared upon a read access and upon any reset event. Hardware ensures that no interrupt event is lost in case there is a new interrupt forced while reading the register. After reading the Interrupt register pin INTN is released for tINTN to guarantee an edge event at pin INTN. The interrupts can be classified into two groups: * Timing critical interrupts which require immediate reaction (SPI clock count failure which needs a new SPI command to be resent immediately, and a BAT failure which needs critical data to be saved immediately into the nonvolatile memory) * Interrupts which do not require an immediate reaction (overtemperature, Ground Shift, CAN and LIN failures, V1, V2 and V3 failures and the wake-ups via CAN, LIN and WAKE. These interrupts will be signalled in Normal mode to the microcontroller once per watchdog period (maximum); this prevents overloading the microcontroller with unexpected interrupt events (e.g. a chattering CAN failure). However, these interrupts are reflected in the Interrupt register UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 35 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 10. Bit 15 and 14 13 12 Interrupt register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 01 1 1 0 read the Interrupt register without writing to the Interrupt Enable register read the Interrupt register and write to the Interrupt Enable register a watchdog overflow during Standby mode has caused an interrupt (interrupt-based cyclic wake-up feature) no interrupt the temperature warning status (TWS) has changed no interrupt the ground shift diagnosis bit (GSD) has changed no interrupt wrong number of CLK cycles (more than, or less than 16) during SPI access no interrupt; SPI access is ignored if the number of CLK cycles does not equal 16 should always be set to logic 0 V1D, V2D or V3D has been cleared no interrupt CAN failure status has changed no interrupt LIN failure status has changed no interrupt a negative edge at WAKE has been detected no interrupt A watchdog restart during watchdog OFF has caused an interrupt no interrupt CAN wake-up event has caused an interrupt no interrupt LIN wake-up event has caused an interrupt no interrupt Function read Interrupt register 11 WTI Watchdog Time-out Interrupt OverTemperature Interrupt Ground Shift Interrupt SPI clock count Failure Interrupt 1 0 10 9 8 OTI GSI SPIFI 1 0 1 0 1 0 7 6 5 4 3 2 VFI CANFI LINFI WI WDRI reserved 0 0 Voltage Failure Interrupt 1 CAN Failure Interrupt LIN Failure Interrupt Wake-up Interrupt Watchdog Restart Interrupt CAN Wake-up Interrupt LIN Wake-up Interrupt 1 0 1 0 1 0 1 0 1 0 CANI LINI 1 0 1 0 UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 36 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 6.13.8 System Configuration register and System Configuration Feedback register These registers allow configuration of the behavior of the SBC, and allow the settings to be read back. Table 11. Bit 15 and 14 13 12 System Configuration register and System Configuration Feedback register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 10 1 0 1 0 11 and 10 9 8 7 and 6 GSTHC RLC V3C[1:0] reserved GND Shift Threshold Control Reset Length Control V3 Control 0 1 0 1[1] 0 11 10 01 00 5 4 V1CMC reserved V1 Current Monitor Control 0 1 0 3 2 1 0 WEN WSC ILEN ILC WAKE Enable[2] WAKE Sample Control INH/LIMP Enable INH/LIMP Control 1 0 1 0 1 0 1 0 [1] [2] Function select System Configuration register read the General Purpose Feedback register 0 read the System Configuration Feedback register read register selected by RRS without writing to System Configuration register read register selected by RRS and write to System Configuration register reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit Vdet(GSD)(CANH) widened threshold Vdet(GSD)(CANH) normal threshold tRSTNL long reset lengthening time selected tRSTNL short reset lengthening time selected Cyclic mode 2; tw(CS) long period; see Figure 13 Cyclic mode 1; tw(CS) short period; see Figure 13 continuously ON OFF reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit an increasing V1 current causes a reset if the watchdog was disabled during Standby mode an increasing V1 current just reactivates the watchdog during Standby mode WAKE pin enabled WAKE pin disabled WAKE mode cyclic sample WAKE mode continuous sample INH/LIMP pin active (see ILC bit) INH/LIMP pin floating INH/LIMP pin HIGH if ILEN bit is set INH/LIMP pin LOW if ILEN bit is set RLC is set automatically with entering Restart mode or Fail-safe mode. This guarantees a safe reset period in case of serious failure situations. External reset spikes are lengthened by the SBC until the programmed reset length is reached. If WEN is not set, the WAKE port is completely disabled. There is no change of the bits EWS and WLS within the System Status register. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 37 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 6.13.9 Physical Layer Control register and Physical Layer Control Feedback register These registers allow configuration of the CAN transceiver and LIN transceiver of the SBC and allow the settings to be read back. Table 12. Bit 15 and 14 13 12 Physical Layer Control register and Physical Layer Control Feedback register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 11 1 0 1 0 11 10 V2C CPNC V2 Control CAN Partial Networking Control 0 1 1 Function select Physical Layer Control register read the General Purpose Feedback register 1 read the Physical Layer Control Feedback register read the register selected by RRS without writing to the Physical Layer Control register read the register selected by RRS and write to Physical Layer Control register V2 is OFF in CAN Off-line mode V2 remains active in CAN Off-line mode CAN transceiver enters On-line Listen mode instead of On-line mode; cleared whenever the SBC enters On-line mode or Active mode On-line Listen mode disabled toff-line long period (extended to toff-line(ext) after wake-up) toff-line short period (extended to toff-line(ext) after wake-up) CAN transmitter is disabled CAN transmitter is enabled TXD signal is forwarded directly to RXD for self-test purposes (loopback behavior); only if CTC = 1 TXD signal is not forwarded to RXD (normal behavior) CAN Active mode (in Normal mode and Flash mode only) CAN Active mode disabled reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit LIN Active mode (in Normal mode and Flash mode only) LIN Active mode disabled up to 10.4 kbit/s (low slope) up to 20 kbit/s (normal) increased LIN driver current capability LIN driver in conformance with the LIN 2.0 standard Wake-up via the LIN-bus enabled Wake-up via the LIN-bus disabled LIN transmitter is disabled LIN transmitter is enabled 0 9 8 7 COTC CTC CRC CAN Off-line Time Control[1] CAN Transmitter Control[2] CAN Receiver Control 1 0 1 0 1 0 6 5 4 3 2 1 0 CMC LMC LSC LDC LWEN LTC CAN Mode Control reserved LIN Mode Control LIN Slope Control LIN Driver Control LIN Wake-up Enable LIN Transmitter Control[3] 1 0 0 1 0 1 0 1 0 1 0 1 0 [1] [2] For the CAN transceiver to enter Off-Line mode from On-line or On-line Listen mode a minimum time without bus activity is needed. This minimum time toff-line is defined by COTC; see Section 6.7.1.4. In case of an RXDC / TXDC interfacing failure the CAN transmitter is disabled without setting CTC. Recovery from such a failure is automatic when CAN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and clearing the CTC bit under software control. All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. UJA1061_6 Product data sheet Rev. 06 -- 9 March 2010 38 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip [3] In case of an RXDC / TXDC interfacing failure the LIN transmitter is disabled without setting LTC. Recovery from such a failure is automatic when LIN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and clearing the LTC bit under software control. 6.13.10 Special Mode register and Special Mode Feedback register These registers allow configuration of global SBC parameters during start-up of a system, and allow the settings to be read back. Table 13. Bit 15 and 14 13 12 Special Mode register and Special Mode Feedback register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 01 0 1 1 0 11 and 10 9 ISDM reserved Initialize Software Development Mode[1] Error-pin Emulation Mode 0 1 0 1 Function select Special Mode register read the Interrupt Enable Feedback register read the Special Mode Feedback register read the register selected by RRS without writing to the Special Mode register read the register selected by RRS and write to the Special Mode register reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit initialization of Software Development mode normal watchdog interrupt, reset monitoring and fail-safe behavior pin EN reflects the status of the CANFD bits: EN is set if CANFD = 0000 (no error) EN is cleared if CANFD is not 0000 (error) 0 7 6 and 5 WDPRE [1:0] reserved Watchdog Prescaler 0 00 01 10 11 4 and 3 V1RTHC [1:0] V1 Reset Threshold Control 11 10 01 00 2 to 0 reserved 0 pin EN behaves as an enable pin; see Section 6.5.2 reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit watchdog prescale factor 1 watchdog prescale factor 1.5 watchdog prescale factor 2.5 watchdog prescale factor 3.5 V1 reset threshold = 0.9 x VV1(nom) V1 reset threshold = 0.7 x VV1(nom)[2] V1 reset threshold = 0.8 x VV1(nom) V1 reset threshold = 0.9 x VV1(nom) reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit 8 ERREM [1] [2] See Section 6.14.1. Not supported in the UJA1061TW/3V3 version. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 39 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 6.13.11 General Purpose registers and General Purpose Feedback registers The UJA1061 offers two 12-bit General Purpose registers (and accompanying General Purpose Feedback registers) with no predefined bit definition. These registers can be used by the microcontroller for advanced system diagnosis, or for storing critical system status information outside the microcontroller. After Power-up General Purpose register 0 will contain a `Device Identification Code' consisting of the SBC type and SBC version. This code is available until it is overwritten by the microcontroller (as indicated by the DIC bit). Table 14. Bit 15, 14 13 12 General Purpose register 0 and General Purpose Feedback register 0 bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 10 1 0 1 0 11 DIC Device Identification Control[1] General Purpose bits[2] 1 0 1 0 [1] [2] Function select General Purpose Feedback register 0 read the General Purpose Feedback register 0 read the System Configuration Feedback register read the register selected by RRS without writing to the General Purpose register 0 read the register selected by RRS and write to the General Purpose register 0 General Purpose register 0 contains user-defined bits General Purpose register 0 contains the Device Identification Code user-defined user-defined 10 to 0 GP0[10:0] The Device Identification Control bit is cleared during power-up of the SBC, indicating that General Purpose register 0 is loaded with the Device Identification Code. Any write access to General Purpose register 0 will set the DIC bit, regardless of the value written to DIC. During power-up the General Purpose register 0 is loaded with a `Device Identification Code' consisting of the SBC type and SBC version, and the DIC bit is cleared. Table 15. Bit 15 and 14 13 12 General Purpose register 1 and General Purpose Feedback register 1 bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 11 1 0 1 0 Function select General Purpose register 1 read the General Purpose Feedback register 1 read the Physical Layer Control Feedback register read the register selected by RRS without writing to the General Purpose register 1 read the register selected by RRS and write to the General Purpose register 1 user-defined user-defined 11 to 0 GP1[11:0] General Purpose bits 1 0 UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 40 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 6.13.12 Register configurations at reset At power-on, Start-up and Restart the setting of the SBC registers is predefined. Table 16. Symbol RSS CWS System Status register: status at reset Name Reset Source Status CAN Wake-up Status Power-on 0000 (power-on reset) 0 (no CAN wake-up) Start-up[1] any value except 1100 Restart[1] 0000 or 0010 or 1100 or 1110 1 if reset is caused by a no change CAN wake-up, otherwise no change 1 if reset is caused by a no change LIN wake-up, otherwise no change 1 if reset is caused by a no change wake-up via pin WAKE, otherwise no change actual status actual status actual status 0 (EN = LOW)[2] no change actual status actual status actual status 0 (EN = LOW)[2] no change LWS LIN Wake-up Status 0 (no LIN wake-up) EWS Edge Wake-up Status 0 (no edge detected) WLS TWS SDMS ENS PWONS [1] [2] Depends on history. WAKE Level Status Temperature Warning Status actual status 0 (no warning) Software Development actual status Mode Status Enable Status Power-on Status 0 (EN = LOW)[2] 1 (power-on reset) In case the ERREM bit in the Special Mode register is 0. Otherwise ENS shows the actual CAN failure status. Table 17. Symbol GSD CANFD LINFD V3D V2D V1D CANMD Table 18. Symbol All Table 19. Symbol All System Diagnosis register: status at reset Name Power-on Start-up actual status actual status actual status actual status actual status actual status actual status Restart actual status actual status actual status actual status actual status actual status actual status Ground Shift Diagnosis 0 (OK) CAN Failure Diagnosis 0000 (no failure) LIN Failure Diagnosis V3 Diagnosis V2 Diagnosis V1 Diagnosis CAN Mode Diagnosis 00 (no failure) 1 (OK) 1 (OK) 0 (fail) 00 (Off-line) Interrupt Enable register and Interrupt Enable Feedback register: status at reset Name all bits Interrupt register: status at reset Name all bits Power-on 0 (no interrupt) Start-up 0 (no interrupt) Restart 0 (no interrupt) Power-on 0 (interrupt disabled) Start-up no change Restart no change UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 41 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 20. Symbol GSTHC RLC V3C V1CMC WEN WSC ILEN System Configuration register and System Configuration Feedback register: status at reset Name GND Shift level Threshold Control Reset Length Control V3 Control Power-on 0 (normal) 0 (short) 00 (off) Start-up no change no change no change no change no change no change see Figure 12 if ILC = 1, otherwise no change no change Restart no change 1 (long) no change no change no change no change 0 (floating) if ILC = 1, otherwise no change no change Fail-safe no change 1 (long) no change no change no change no change 1 (active) V1 Current Monitor 0 (watchdog Control restart) Wake Enable Wake Sample Control INH/LIMP Enable 1 (enabled) 0 (control) 0 (floating) ILC Table 21. Symbol V2C CPNC INH/LIMP Control 0 (LOW) 0 (LOW) Physical Layer Control register and Physical Layer Control Feedback register: status at reset Name V2 Control Power-on 0 (auto) Start-up no change Restart no change Fail-safe 0 (auto) 0 (On-line Listen mode disabled) CAN Partial 0 (On-line Listen Networking Control mode disabled) 0 if reset is caused no change by a CAN wake-up, otherwise no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change COTC CTC CRC CMC LMC LSC LDC LWEN LTC CAN Off-line Time Control CAN Transmitter Control CAN Receiver Control 1 (long) 0 (on) 0 (normal) no change no change no change no change no change no change no change no change no change CAN Mode Control 0 (Active mode disabled) LIN Mode Control LIN Slope Control LIN Driver Control LIN Wake-up Enable LIN Transmitter Control 0 (Active mode disabled) 0 (normal) 0 (LIN 2.0) 1 (enabled) 0 (on) UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 42 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 22. Symbol ISDM ERREM WDPRE V1RTHC Table 23. Symbol DIC GP0[10:7] GP0[6:0] Special Mode register: status at reset Name Initialize Software Development Mode Error pin emulation mode Watchdog Prescale Factor V1 Reset Threshold Control Power-on 0 (no) 0 (EN function) 00 (factor 1) 00 (90 %) Start-up no change no change no change no change Restart no change no change no change 00 (90 %) General Purpose register 0 and General Purpose Feedback register 0: status at reset Name Device Identification Control general purpose bits 10 to 7 (version) general purpose bits 6 to 0 (SBC type) Power-on 0 (Device ID) Mask version 000 0001 (UJA1061) Start-up no change no change no change Restart no change no change no change Table 24. Symbol GP1[11:0] General Purpose register 1 and General Purpose Feedback register 1: status at reset Name general purpose bits 11 to 0 Power-on 0000 0000 0000 Start-up no change Restart no change 6.14 Test modes 6.14.1 Software Development mode The Software Development mode is intended to support software developers in writing and pretesting application software without having to work around watchdog triggering and without unwanted jumps to Fail-safe mode. In Software Development mode the following events do not force of a system reset: * * * * Watchdog overflow in Normal mode Watchdog window miss Interrupt time-out Elapsed start-up time However, in case of a watchdog trigger failure the reset source information is still provided in the System Status register as if there was a real reset event. The exclusion of watchdog related resets allows simplified software testing, because possible problems in the watchdog triggering can be indicated by interrupts instead of resets. The SDM bit does not affect the watchdog behavior in Standby and Sleep mode. This allows the cyclic wake-up behavior to be evaluated during Standby and Sleep mode of the SBC. All transitions to Fail-safe mode are disabled. This allows working with an external emulator that clamps the reset line LOW in debugging mode. A V1 undervoltage of more than tV1(CLT) is the only exception that results in entering Fail-safe mode (to protect the SBC). Transitions from Start-up mode to Restart mode are still possible. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 43 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip There are two possibilities to enter Software Development mode. One is by setting the ISDM bit via the Special Mode register; possible only once after a first battery connection while the SBC is in Start-up mode. The second possibility to enter Software Development mode is by applying the correct Vth(TEST) input voltage at pin TEST before the battery is applied to pin BAT42. To stay in Software Development mode the SDM bit in the Mode register has to be set with each Mode register access (i.e. watchdog triggering) regardless of how Software Development mode was entered. The Software Development mode can be exited at any time by clearing the SDM bit in the Mode register. Reentering the Software Development mode is only possible by reconnecting the battery supply (pin BAT42), thereby forcing a new power-on reset. 6.14.2 Forced Normal mode For system evaluation purposes the UJA1061 offers the Forced Normal mode. This mode is strictly for evaluation purposes only. In this mode the characteristics as defined in Section 9 and Section 10 cannot be guaranteed. In Forced normal mode the SBC behaves as follows: * * * * * * SPI access (writing and reading) is blocked Watchdog disabled Interrupt monitoring disabled Reset monitoring disabled Reset lengthening disabled All transitions to Fail-safe mode are disabled, except a V1 undervoltage for more than tV1(CLT) performed until V1 is restored (normal behavior), and the SBC stays in Forced Normal mode; in case of a continuous overload at V1 > tV1(CLT) Fail-safe mode is entered * V1 is started with the long reset time tRSTNL. In case of a V1 undervoltage, a reset is * * * * * * V2 is on; overload protection active V3 is on; overload protection active CAN and LIN are in Active mode and cannot switch to Off-line mode INH/LIMP pin is HIGH SYSINH is HIGH EN pin at same level as RSTN pin Forced Normal mode is activated by applying the correct Vth(TEST) input voltage at the TEST pin during first battery connection. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 44 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 7. Limiting values Table 25. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol VBAT42 VBAT14 Parameter BAT42 supply voltage load dump; t 500 ms BAT14 supply voltage VBAT42 VBAT14 - 1 V continuous load dump; t 500 ms VDC(n) DC voltages on pins V1 and V2 V3 and SYSINH WAKE INH/LIMP CANH, CANL, RTH, RTL LIN and RTLIN; with respect to any other pin TXDC, RXDC, TXDL, RXDL, SDO, SDI, SCK, SCS, RSTN, INTN and EN TEST Vtrt IWAKE Tstg Tamb Tvj Vesd transient voltage DC current at pin WAKE storage temperature ambient temperature virtual junction temperature electrostatic discharge voltage HBM at pins CANH, CANL, RTH, RTL, LIN, RTLIN, WAKE, BAT42, V3; with respect to GND at any other pin MM; at any pin [1] [2] Only relevant if VWAKE < VGND - 0.3 V; current will flow into pin GND. In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + Pd x Rth(vj-amb), where Rth(vj-amb) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (Pd) and ambient temperature (Tamb). Human Body Model (HBM): C = 100 pF; R = 1.5 k. ESD performance according to IEC 61000-4-2 (C = 150 pF, R = 330 ) of pins CANH, CANL, RTH, RTL, LIN, RTLIN, WAKE, BAT42 and V3 with respect to GND was verified by an external test house. Following results were obtained: a) equal or better than 6 kV (unaided). b) equal or better than 20 kV (using external ESD protection: NXP Semiconductors PESD1CAN and PESD1LIN diode). [5] Machine Model (MM): C = 200 pF; L = 0.75 H; R = 10 . [5] [2] [3] [4] Conditions Min -0.3 -0.3 -0.3 -1.5 -1.5 -0.3 -60 Max +60 60 +33 45 +5.5 VBAT42 + 0.3 +60 VBAT42 + 0.3 +60 Unit V V V V V V V V V -0.3 VV1 + 0.3 V -0.3 -150 [1] +15 +100 +150 +125 +150 +8.0 V V mA C C C kV at pins CANH, CANL and LIN; in accordance with ISO 7637-3 -15 -55 -40 -40 -8.0 -2.0 -200 +2.0 +200 kV V [3] [4] UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 45 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 8. Thermal characteristics V1 dissipation V2 dissipation V3 dissipation other dissipation Tvj 6 K/W 20 K/W 23 K/W 6 K/W 6 K/W Tcase(heat sink) Rth(c-a) Tamb 001aac327 Fig 15. Thermal model of the HTSSOP32 package UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 46 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 9. Static characteristics Table 26. Static characteristics[1] Tvj = -40 C to +150 C; VBAT42 = 5.5 V to 52 V;VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Supply; pin BAT42 IBAT42 BAT42 supply current V1, V2 and V3 off; CAN and LIN in Off-line mode; OTIE = BATFIE = 0; ISYSINH = IWAKE = IRTLIN = ILIN = 0 mA VBAT42 = 8.1 V to 52 V VBAT42 = 5.5 V to 8.1 V IBAT42(add) additional BAT42 supply current V1 and / or V2 on; ISYSINH = 0 mA V3 in cyclic mode; IV3 = 0 mA V3 continuously on; IV3 = 0 mA Tvj warning enabled; OTIE = 1 CAN in Active mode; CMC = 1 LIN in Active mode; LMC = 1; VTXDL = VV1; IRTLIN = ILIN = 0 mA LIN in Active mode; LMC = 1; VTXDL = 0 V (t < tLIN(dom)(det)); IRTLIN = ILIN = 0 mA; VBAT42 = 12 V LIN in Active mode; LMC = 1; VTXDL = 0 V (t < tLIN(dom)(det)); IRTLIN = ILIN = 0 mA; VBAT42 = 27 V VPOR(BAT42) BAT42 voltage level for Power-on reset status bit change for setting PWONS PWONS = 0; VBAT42 falling for clearing PWONS PWONS = 1; VBAT42 rising Supply; pin BAT14 VBAT14 BAT14 supply voltage normal output current capability at V1 high output current capability at V1 IBAT14 BAT14 supply current V1 and V2 off; CAN and LIN in Off-line mode; ILEN = CSC = 0; IINH/LIMP = 0 mA 9 6 2 27 8 5 V V A 4.75 5.5 V 4.45 5 V 50 70 53 0 30 20 100 650 70 93 76 1 50 40 400 1300 A A A A A A A A Parameter Conditions Min Typ Max Unit - 1.5 5 mA - 3 10 mA UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 47 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 26. Static characteristics[1] ...continued Tvj = -40 C to +150 C; VBAT42 = 5.5 V to 52 V;VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. Symbol IBAT14(add) Parameter additional BAT14 supply current Conditions V1 on; IV1 = 0 mA V1 on; IV1 = 0 mA; VBAT14 = 12 V V2 on; IV2 = 0 mA V2 on; IV2 = 0 mA; VBAT14 = 12 V INH/LIMP enabled; ILEN = 1; IINH/LIMP = 0 mA CAN in Active mode; CMC = 1; ICANH = ICANl = 0 mA; VTXD = 0 V Differential mode Single-ended mode CAN in Active mode; CMC = 1; VTXD = VV1 Differential mode Single-ended mode Voltage source; pin Vo(V1) V1[2]; see also Figure 16 to 22 VBAT14 = 5.5 V to 18 V; IV1 = -120 mA to -5 mA; Tj = 25 C VBAT14 = 14 V; IV1 = -5 mA; Tj = 25 C VV1 supply voltage regulation load regulation voltage drift with temperature Vdet(UV)(V1) undervoltage detection and reset activation level VBAT14 = 9 V to 16 V; IV1 = -5 mA; Tj = 25 C VBAT14 = 14 V; IV1 = -50 mA to -5 mA; Tj = 25 C VBAT14 = 14 V; IV1 = -5 mA; Tj = -40 C to +150 C VBAT14 = 14 V; V1RTHC = 00 or 11 VBAT14 = 14 V; V1RTHC = 01 VBAT14 = 14 V; V1RTHC = 10 Vrel(UV)(V1) undervoltage detection release level VBAT14 = 14 V; V1RTHC = 00 or 11 VBAT14 = 14 V; V1RTHC = 01 VBAT14 = 14 V; V1RTHC = 10 VUV(VFI) undervoltage level for VBAT14 = 14 V; VFIE = 1 generating a VFI interrupt [3] Min - Typ 200 150 200 200 1 Max 300 200 320 250 2 Unit A A A A A - 10 13 20 25 mA mA VV1(nom) - 0.1 VV1(nom) - 0.025 0.90 x VV1(nom) 0.80 x VV1(nom) 0.70 x VV1(nom) 0.90 x VV1(nom) 5 8 VV1(nom) 10 15 VV1(nom) + 0.1 VV1(nom) + 0.025 25 25 200 0.95 x VV1(nom) 0.85 x VV1(nom) 0.75 x VV1(nom) 0.97 x VV1(nom) mA mA V output voltage VV1(nom) 1 5 0.92 x VV1(nom) 0.82 x VV1(nom) 0.72 x VV1(nom) 0.94 x VV1(nom) 0.84 x VV1(nom) 0.74 x VV1(nom) 0.93 x VV1(nom) V mV mV ppm/K V V V V V V V UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 48 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 26. Static characteristics[1] ...continued Tvj = -40 C to +150 C; VBAT42 = 5.5 V to 52 V;VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. Symbol IthH(V1) Parameter undercurrent threshold for watchdog enable undercurrent threshold for watchdog disable output current capability VBAT14 = 9 V to 27 V; VV1 = 0.05 x VV1(nom) VBAT14 = 9 V to 27 V; V1 shorted to GND VBAT14 = 8 V to 9 V; VV1 = 0.05 x VV1(nom) VBAT14 = 5.5 V to 8 V; VV1 = 0.05 x VV1(nom) Zds(on) regulator impedance between pins BAT14 and V1 output voltage VBAT14 = 4 V to 5 V Conditions Min -10 Typ -5 Max -2 Unit mA IthL(V1) -6 -3 -1.5 mA IV1 -200 -200 - -135 -110 3 -120 -120 -150 5 mA mA mA mA Voltage source; pin V2[4] Vo(V2) VBAT14 = 9 V to 16 V; IV2 = -50 mA to -5 mA VBAT14 = 14 V; IV2 = -10 mA; Tj = 25 C VV2 supply voltage regulation load regulation voltage drift with temperature IV2 output current capability VBAT14 = 9 V to 16 V; IV2 = -10 mA; Tj = 25 C VBAT14 = 14 V; IV2 = -50 mA to -5 mA; Tj = 25 C VBAT14 = 14 V; IV2 = -10 mA; -40 C < Tj < 150 C VBAT14 = 9 V to 27 V; VV2 = 300 mV VBAT14 = 9 V to 27 V; V2 shorted to GND VBAT14 = 6 V to 8 V; VV2 = 300 mV VBAT14 = 5.5 V; VV2 = 300 mV Vdet(UV)(V2) undervoltage detection threshold VBAT42 to VV3 voltage drop overload current detection threshold VBAT14 = 14 V [3] 4.8 4.95 -200 -300 4.5 5.0 5.0 1 4.6 5.2 5.05 25 50 200 -120 -80 -50 4.8 V V mV mV ppm/K mA mA mA mA V Voltage source; pin V3 VBAT42-V3(drop) Idet(OL)(V3) VBAT42 = 9 V to 52 V; IV3 = -20 mA VBAT42 = 9 V to 52 V -165 1.0 -60 V mA UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 49 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 26. Static characteristics[1] ...continued Tvj = -40 C to +150 C; VBAT42 = 5.5 V to 52 V;VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. Symbol VBAT42-SYSINH(drop) |IL| VBAT14-INH(drop) Parameter VBAT42 to VSYSINH voltage drop leakage current Conditions ISYSINH = -0.2 mA VSYSINH = 0 V Min 0.8 Typ 1.0 0.7 1.2 Max 2.0 5 1.0 2.0 4 5 Unit V A V V mA A System inhibit output; pin SYSINH Inhibit / limp-home output; pin INH/LIMP VBAT14 to VINH voltage IINH/LIMP = -10 A; drop ILEN = ILC = 1 IINH/LIMP = -200 A; ILEN = ILC = 1 Io(INH/LIMP) |IL| output current capability leakage current VINH/LIMP = 0.4 V; ILEN = 1; ILC = 0 VINH/LIMP = 0 V to VBAT14; ILEN = 0 Wake input; pin WAKE Vth(WAKE) IWAKE(pu) VIH(th) VIL(th) Rpd(SCK) Rpu(SCS) ILI(SDI) WAKE voltage threshold pull-up input current HIGH-level input threshold voltage LOW-level input threshold voltage pull-down resistor at pin SCK pull-up resistor at pin SCS input leakage current at pin SDI HIGH-level output current LOW-level output current OFF-state output leakage current HIGH-level output current LOW-level output current LOW-level output voltage HIGH-level input threshold voltage All information provided in this document is subject to legal disclaimers. 2.0 VWAKE = 0 V -25 3.3 - 5.2 -1.3 V A Serial peripheral interface inputs; pins SDI, SCK and SCS 0.7 x VV1 -0.3 VSCK = 2 V; VV1 2 V VSCS = 1 V; VV1 2 V VSDI = 0 V to VV1 50 50 -5 130 130 VV1 + 0.3 V 0.3 x VV1 V 400 400 +5 k k A Serial peripheral interface data output; pin SDO IOH IOL ILO(off) VO = VV1 - 0.4 V; VSCS = 0 V VO = 0.4 V; VSCS = 0 V VO = 0 V to VV1; VSCS = VV1 -50 1.6 -5 -1.6 20 +5 mA mA A Reset output with clamping detection; pin RSTN IOH IOL VOL VIH(th) VRSTN = 0.7 x VV1(nom) VRSTN = 0.9 V VV1 = 1.5 V to 5.5 V; pull-up resistor to V1 = 4 k -1000 1 0 -50 5 A mA 0.2 x VV1 V VV1 + 0.3 V 0.7 x VV1 - UJA1061_6 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 50 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 26. Static characteristics[1] ...continued Tvj = -40 C to +150 C; VBAT42 = 5.5 V to 52 V;VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. Symbol VIL(th) Parameter LOW-level input threshold voltage HIGH-level output current LOW-level output current LOW-level output voltage LOW-level output current HIGH-level input voltage LOW-level input voltage TXDC pull-up resistor VTXDC = 0 V HIGH-level output current LOW-level output current differential receiver threshold voltage VOH = VV1 - 0.4 V VOL = 0.4 V VOH = VV1 - 0.4 V VOL = 0.4 V IOL = 20 A; VV1 = 1.2 V Conditions Min -0.3 Typ Max +0.3 x VV1 -1.6 20 0.4 Unit V Enable output; pin EN IOH IOL VOL -20 1.6 0 mA mA V Interrupt output; pin INTN IOL VOL = 0.4 V 1.6 15 mA CAN transmit data input; pin TXDC VIH VIL RTXDC(pu) IOH IOL 0.7 x VV1 -0.3 5 -25 1.6 12 VV1 + 0.3 V +0.3 x VV1 25 -1.6 25 V k mA mA CAN receive data output; pin RXDC Fault-tolerant CAN-bus lines; pins CANH and CANL Vdif(CANH-CANL) Active mode, On-line, Partial Networking or On-Line Listen mode; VV2 = 5 V; no failures and bus failures H//, L//, HxGND and LxVCC Active mode, On-line, Partial Networking or On-Line Listen mode; VV2 = 5 V; bus failures LxGND, LxBAT and HxL Active mode, On-line, Partial Networking or On-Line Listen mode; VV2 = 5 V; bus failures HxBAT and HxVCC Active mode, On-line, Partial Networking or On-Line Listen mode; VV2 = 5 V Active mode; VV2 = 5 V SPI bit GSTHC = logic 0 SPI bit GSTHC = logic 1 -1.25 -2.0 -0.75 -1.5 -0.25 -1.0 V V -3.5 -3.2 -2.9 V Vse(CANH) pin CANH single ended receiver threshold voltage pin CANL single ended receiver threshold voltage detection threshold voltage for bus failures HxBAT and LxBAT pin CANH ground shift detection threshold voltage 1.5 1.7 1.85 V Vse(CANL) 3.15 3.3 3.45 V Vdet(HxBAT), Vdet(LxBAT) 6.5 7.1 8.0 V Vdet(GSD)(CANH) UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 51 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 26. Static characteristics[1] ...continued Tvj = -40 C to +150 C; VBAT42 = 5.5 V to 52 V;VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Vwu(CANH) Vwu(CANL) Vwu(CANH-CANL) VO(reces) Parameter pin CANH wake-up threshold voltage pin CANL wake-up threshold voltage wake-up threshold difference voltage CANH recessive output voltage Conditions off-line off-line CANH to CANL; off-line Active mode, On-line, Partial Networking or On-Line Listen mode; VV2 = 4.75 V to 5.25 V; VTXDC = VV2; RRTH < 4 k Active mode, On-line, Partial Networking or On-Line Listen mode; VV2 = 4.75 V to 5.25 V; VTXDC = VV2; RRTL < 4 k Active mode, On-line, Partial Networking or On-Line Listen mode; VTXDC = 0 V; VV2 = 5 V; ICANH = -40 mA Active mode, On-line, Partial Networking or On-Line Listen mode; VTXDC = 0 V; VV2 = 5 V; ICANL = 40 mA Active mode; VCANH = 0 V; VTXDC = 0 V; VV2 = 5 V Auto mode; VCANH = 0 V; VBAT14 = 14 V IO(CANL) pin CANL output current Active mode; VCANL = 5 V; VTXDC = 0 V; VV2 = 5 V Auto mode; VCANL = 14 V; VBAT14 = 14 V CAN termination resistor (pin RTH) Rsw(RTH) switch-on resistance measured between RTH and GND; Active mode, On-line or Selective Sleep; Io = 10 mA; VTXDC = 5 V off-line; IO = 100 A Active mode; VRTH = VCANH = VV2 = 5 V 40 100 Min 2.5 1.1 0.8 Typ 3.2 1.8 1.4 Max 3.9 2.5 0.2 Unit V V V V CANL recessive output voltage VV2 - 0.2 - - V VO(dom) CANH dominant output voltage VV2 - 1.4 - - V CANL dominant output voltage - - 1.4 V IO(CANH) pin CANH output current -110 45 - -75 -0.25 75 0 -45 110 - mA A mA A VO(RTH) IO(RTH) output voltage pin CANH output current during bus failure switch-on resistance - 0.7 95 1.0 - V A CAN termination resistor (pin RTL) Rsw(RTL) Active mode, On-line or Selective Sleep; Io = 10 mA; VTXDC = 5 V; VV2 = 5 V off-line; VRTL = 0 V during bus failure at CANL; Active mode; VRTL = VCANL = 0 V; VV2 = 5 V UJA1061_6 All information provided in this document is subject to legal disclaimers. - 40 100 IO(RTL) output current -1.50 - -0.65 -95 -0.1 - mA A (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 52 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 26. Static characteristics[1] ...continued Tvj = -40 C to +150 C; VBAT42 = 5.5 V to 52 V;VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. Symbol VIL VIH RTXDL(pu) IOH IOL LIN-bus line; pin LIN Vo(dom) LIN dominant output voltage Active mode; VBAT42 = 7 V to 18 V; LDC = 0; t < tTXDL(dom)(dis); VTXDL = 0 V; RBAT42-LIN = 500 Active mode; VBAT42 = 7.6 V to 18 V; LDC = 1; t < tTXDL(dom)(dis); VTXDL = 0 V; ILIN = 40 mA ILIH HIGH-level input leakage current LOW-level input leakage current short-circuit output current VLIN = VBAT42; VTXDL = VV1 VBAT42 = 8 V; VLIN = 8 V to 18 V; VTXDL = VV1 VBAT42 = 12 V; VLIN = 0 V; VTXDL = VV1 Active mode; VLIN = VBAT42 = 12 V; VTXDL = 0 V; t < tTXDL(dom)(dis); LDC = 0 Active mode; VLIN = VBAT42 = 18 V; VTXDL = 0 V; t < tTXDL(dom)(dis); LDC = 0 Vth(dom) Vth(reces) Vth(hyst) Vth(cen) Cin IL receiver dominant state receiver recessive state receiver threshold voltage hysteresis receiver threshold voltage centre input capacitance leakage current VLIN = 0 V to 18 V; VBAT42 = 0 V VLIN = 0 V to 18 V; VBAT42 = VGND = 12 V (loss of ground) UJA1061_6 All information provided in this document is subject to legal disclaimers. Parameter LOW-level input voltage HIGH-level input voltage TXDL pull-up resistor HIGH-level output current LOW-level output current Conditions Min -0.3 Typ - Max Unit LIN transmit data input; pin TXDL 0.3 x VV1 V VV1 + 0.3 V 25 -1.6 20 k mA mA 0.7 x VV1 VTXDL = 0 V VRXDL = VV1 - 0.4 V VRXDL = 0.4 V 5 -50 1.6 12 - LIN receive data output; pin RXDL 0 - 0.20 x VBAT42 V 0.7 1.4 2.1 V -10 -10 -100 27 0 40 +10 +10 60 A A A mA ILIL Io(sc) 40 60 90 mA VBAT42 = 7 V to 27 V VBAT42 = 7 V to 27 V VBAT42 = 7 V to 27 V VBAT42 = 7 V to 27 V [3] 0.6 x VBAT42 0.05 x VBAT42 0.475 x VBAT42 -5 -10 0.500 x VBAT42 0 - 0.4 x VBAT42 0.175 x VBAT42 0.525 x VBAT42 10 +5 +10 V V V V pF A A (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 53 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 26. Static characteristics[1] ...continued Tvj = -40 C to +150 C; VBAT42 = 5.5 V to 52 V;VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. Symbol VRTLIN Parameter RTLIN output voltage Conditions Active mode; IRTLIN = -10 A; VBAT42 = 7 V to 27 V Off-line mode; IRTLIN = -10 A; VBAT42 = 7 V to 27 V VRTLIN RTLIN load regulation Active mode; IRTLIN = -10 A to -10 mA; VBAT42 = 7 V to 27 V RTLIN pull-up current Active mode; VRTLIN = VLIN = 0 V (t > tLIN(dom)(det)) Off-line mode; VRTLIN = VLIN = 0 V (t < tLIN(dom)(det)) ILIL LOW-level input leakage current Off-line mode; VRTLIN = VLIN = 0 V (t > tLIN(dom)(det)) for entering Software Development mode; Tj = 25 C for entering Forced Normal mode; Tj = 25 C R(pd)TEST Tj(warn) pull-down resistor high junction temperature warning level between pin TEST and GND Temperature detection 160 175 190 C Min VBAT42 - 1.0 VBAT42 - 1.2 Typ VBAT42 - 0.7 VBAT42 - 1.0 0.65 Max VBAT42 - 0.2 2 Unit V V V LIN-bus termination resistor connection; pin RTLIN IRTLIN(pu) -150 -60 -35 A -150 -60 -35 A -10 0 +10 A TEST input; pin TEST Vth(TEST) input threshold voltage 1 2 2 5 10 4 8 13.5 8 V V k [1] All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at Tamb = 125 C on wafer level (pretesting). Cased products are 100 % tested at Tamb = 25 C (final testing). Both pretesting and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. VV1(nom) is 3.3 V or 5 V, depending on the SBC version. Not tested in production. V2 internally supplies the SBC CAN transceiver. The supply current needed for the CAN transceiver reduces the pin V2 output capability. The performance of the CAN transceiver can be impaired if V2 is also used to supply other circuitry while the CAN transceiver is in use. [2] [3] [4] UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 54 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 6 VV1 (V) type 5V0 5 015aaa055 4 IV1 = -100 A -50 mA -120 mA -250 mA type 3V3 3 2 2 3 4 5 6 VBAT14 (V) 7 a. Tj = 25 C. 6 VV1 (V) type 5V0 5 015aaa056 4 3 IV1 = -100 A -50 mA -120 mA -250 mA type 3V3 2 2 3 4 5 6 VBAT14 (V) 7 b. Tj = 150 C. Fig 16. V1 output voltage (dropout) as a function of battery voltage UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 55 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 10 IBAT14 - IV1 (mA) 8 Tj = +150 C 001aaf246 Tj = -40 C +25 C +150 C 6 4 VBAT14 = 8 V(1) 2 5.5 V(2) 0 0 -50 -100 -150 -200 -250 +25 C -40 C IV1 (mA) (1) Types 5V0 and 3V3. (2) Type 5V0 only. a. At Tj = -40 C, +25 C and +150 C. 5 IBAT14 - IV1 (mA) 4 001aaf247 3 VBAT14 = 9 V to 27 V(1) 2 5.5 V(2) 1 0 0 -50 -100 -150 -200 IV1 (mA) -250 (1) Types 5V0 and 3V3. (2) Type 3V3 only. b. At Tj = -40 C to +150 C. Fig 17. V1 quiescent current as a function of output current UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 56 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 6 VV1 (V) 4 type 3V3 type 5V0 015aaa057 2 0 0 -40 -80 -120 IV1 (mA) -160 VBAT14 = 9 V to 27 V. Tj = 25 C to 125 C. Fig 18. V1 output voltage as a function of output current 160 PSRR (dB) 120 VBAT14 = 14 V Tj = 25 C 14 V 80 5.5 V 5.5 V(1) 40 150 C 25 C to 150 C 150 C 001aaf248 0 1 10 102 f (Hz) 103 IV1 = -120 mA. (1) Type 5V0 only. Fig 19. V1 power supply ripple rejection as a function of frequency UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 57 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 16 VBAT14 (V) 12 VBAT14 001aaf250 200 VV1 (mV) 100 8 VV1 0 4 0 100 200 300 400 t (s) -100 500 IV1 = -5 mA; C = 1 F; ESR = 0.01 ; Tj = 25 C. a. Line transient response -75 IV1 (mA) -25 IV1 001aaf251 400 VV1 (mV) 200 25 VV1 0 75 0 100 200 300 400 t (s) -200 500 VBAT14 = 14 V; C = 1 F; ESR = 0.01 ; Tj = 25 C. b. Load transient response Fig 20. V1 transient response as a function of time UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 58 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 1 ESR () 10-1 001aaf249 10-2 stable operation area unstable operation area 10-3 0 -40 -80 IV1 (mA) -120 Fig 21. V1 output stability related to ESR value of output capacitor UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 59 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip BAT42 BAT14 100 nF V1 Iload = 30 mA SBC 100 nF 47 F/ 0.1 Rload VBAT 100 F/ 0.1 GND 001aaf572 a. Switch-on test circuit. 6 VV1 (V) 4 VBAT = 8 V 015aaa058 type 5V0 type 3V3 2 VBAT = 5.5 V VBAT = 12 V 0 0 0.4 0.8 1.2 1.6 t (ms) 2.0 b. Behavior at Tj = 25 C. 6 VV1 (V) 4 VBAT = 8 V type 3V3 015aaa059 type 5V0 2 VBAT = 5.5 V VBAT = 12 V 0 0 0.4 0.8 1.2 1.6 t (ms) 2.0 c. Behavior at Tj = 85 C. Fig 22. Switch-on behavior of VV1 UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 60 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 10. Dynamic characteristics Table 27. Dynamic characteristics[1] Tvj = -40 C to + 150 C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Tcyc tlead tlag tSCKH tSCKL tsu th tDOV tSSH tt(rec-dom) Parameter clock cycle time enable lead time enable lag time clock HIGH time clock LOW time input data setup time input data hold time output data valid time pin SDO; CL = 10 pF SPI select HIGH time output transition time between 10 % to 90 %; recessive to dominant RCAN_L = RCAN_H = 125 ; CCAN_L = CCAN_H = 1 nF; see Figure 23 and Figure 24 output transition time between 10 % to 90 %; dominant to recessive RCAN_L = RCAN_H = 125 ; CCAN_L = CCAN_H = 1 nF; see Figure 23 and Figure 24 propagation delay TXDC to RXDC (HIGH to LOW transition) propagation delay TXDC to RXDC (LOW to HIGH transition) bus failure detection time between 10 % to 90 %; RCAN_L = RCAN_H = 125 ; CCAN_L = CCAN_H = 1 nF; see Figure 23 and Figure 24 between 10 % to 90 %; RCAN_L = RCAN_H = 125 ; CCAN_L = CCAN_H = 1 nF; see Figure 23 and Figure 24 bus failure HxBAT; Active mode, On-line and Selective Sleep mode; VV2 = 5 V bus failure HxVCC bus failures LxGND and HxL bus failure LxBAT; Active mode, On-line and Selective Sleep mode; VV2 = 5 V continuously dominant clamped CAN-bus detection time (start after detecting HxVCC); Active mode, On-line and Selective Sleep mode; VV2 = 5 V UJA1061_6 Conditions Min 27)[2] 960 Typ 0.4 Max 400 - Unit ns ns ns ns ns ns ns ns ns s Serial peripheral interface timing; pins SCS, SCK, SDI and SDO (see Figure clock is low when SPI select falls clock is low when SPI select rises 240 240 480 480 80 400 480 0.3 CAN transceiver (pins CANL, CANH, TXDC and RXDC) tt(dom-rec) 0.3 0.6 - s tPHL - - 1.5 s tPLH - 1.2 1.9 s tBUS(fail)(det) 7 - 38 s 1.6 0.3 0.3 - 8.0 1.6 1.6 ms ms ms 0.3 - 1.6 ms All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 61 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 27. Dynamic characteristics[1] ...continued Tvj = -40 C to + 150 C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Conditions bus failure HxBAT bus failure HxVCC bus failures LxGND and HxL; Active mode, On-line and Selective Sleep mode; VV2 = 5 V bus failures LxGND and HxL bus failure LxBAT; Active mode, On-line and Selective Sleep mode; VV2 = 5 V continuously dominant clamped CAN-bus Active mode, On-line and Selective Sleep mode; VV2 = 5 V tTXDC(dom) TXDC permanent Active mode, On-line and dominant disable time Selective Sleep mode; VV2 = 5 V; TXDC = logic 0 V minimum dominant time first pulse for wake-up on pins CANH, CANL minimum recessive time pulse (after first dominant) for wake-up on pins CANH, CANL off-line Min 125 0.3 7 Typ Max 750 1.6 38 Unit s ms s tBUS(fail)(recover) bus failure recovery time 0.3 125 - 1.6 750 ms s 1 - 5 s 1.5 - 6 ms tCANH(d1), tCANL(d1) 7 - 38 s tCANH(rec), tCANL(rec) off-line 3 - 10 s tCANH(d2), tCANL(d2) minimum dominant off-line time second pulse for wake-up on pins CANH, CANL CANL dominant time entering Normal mode and TXDC goes dominant VCANL > 8 V, first dominant bit after entering Active mode 0 - 4 s tCANL(dom) 3 - 10 s ttimeout time-out period On-line Listen mode between wake-up message and confirm message required recessive or dominant time for entering off-line On-line or Selective Sleep mode; COTC = logic 0; CMC = logic 0 On-line or Selective Sleep mode; COTC = logic 1; CMC = logic 0 115 - 285 ms toffline 50 - 66 ms 200 - 265 ms toff-line(ext) extended minimum time before entering Off-line mode On-line or On-line Listen mode after CAN wake-up event; TXDC = VV1; V2D = 1; no bus activity 400 - 530 ms UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 62 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 27. Dynamic characteristics[1] ...continued Tvj = -40 C to + 150 C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. Symbol tCANH, tCANL Parameter Conditions Min 20 Typ Max 80 Unit s ground shift sampling Active mode, On-line and time required for Selective Sleep mode; CANH, CANL voltage VV2 = 5 V; TXDC recessive level pulse count difference between CANH and CANL for failure detection bus failures H//, L//, HxGND and LxVCC; Active mode, On-line and Selective Sleep mode; VV2 = 5 V tPC - 4 - pulses dominant pulse count bus failures H//, L//, HxGND on CANH and CANL and LxVCC; Active mode, for failure recovery On-line and Selective Sleep mode; VV2 = 5 V LIN transceiver; pins LIN, TXDL and RXDL[3] 1 duty cycle 1 Vth(reces)(max) = 0.744 x VBAT42; Vth(dom)(max) = 0.581 x VBAT42; LSC = 0; tbit = 50 s; VBAT42 = 7 V to 18 V Vth(reces)(min) = 0.422 x VBAT42; Vth(dom)(min) = 0.284 x VBAT42; LSC = 0; tbit = 50 s; VBAT42 = 7.6 V to 18 V Vth(reces)(max) = 0.778 x VBAT42; Vth(dom)(max) = 0.616 x VBAT42; LSC = 1; tbit = 96 s; VBAT42 = 7 V to 27 V Vth(reces)(min) = 0.389 x VBAT42; Vth(dom)(min) = 0.251 x VBAT42; LSC = 1; tbit = 96 s; VBAT42 = 7.6 V to 27 V CRXDL = 20 pF rising edge with respect to falling edge; CRXDL = 20 pF Off-line mode [4] - 4 - pulses 0.396 - - 2 duty cycle 2 [5] - - 0.581 3 duty cycle 3 [4] 0.417 - - 4 duty cycle 4 [5] - - 0.590 tp(rx) tp(rx)(sym) tBUS(LIN) propagation delay of receiver symmetry of receiver propagation delay minimum dominant time for wake-up of the LIN-transceiver continuously dominant clamped LIN-bus detection time continuously dominant clamped LIN-bus recovery time -2 30 - 6 +2 150 s s s tLIN(dom)(det) Active mode; LIN = 0 V 40 - 160 ms tLIN(dom)(rec) Active mode 0.8 - 2.2 ms tTXDL(dom)(dis) TXDL permanent Active mode; TXDL = 0 V dominant disable time 20 - 80 ms UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 63 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 27. Dynamic characteristics[1] ...continued Tvj = -40 C to + 150 C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. Symbol tBAT42(L) Parameter BAT42 LOW time for setting PWONS V1 clamped LOW time during ramp-up of V1 V2 clamped LOW time during ramp-up of V2 cyclic sense period cyclic sense on-time Start-up mode; V1 active Conditions Min 5 Typ Max 20 Unit s Battery monitoring Power supply V1; pin V1 tV1(CLT) 229 283 ms Power supply V2; pin V2 tV2(CLT) V2 active 28 36 ms Power supply V3; pin V3 tW(CS) ton(CS) V3C = 10; see Figure 13 V3C = 11; see Figure 13 V3C = 10; see Figure 13 V3C = 11; see Figure 13 Wake-up input; pin WAKE tWU(ipf) tsu(CS) Watchdog tWD(ETP) earliest watchdog trigger point latest watchdog trigger point programmed Nominal Watchdog Period (NWP); Normal mode programmed nominal watchdog period; Normal mode, Standby mode and Sleep mode watchdog time-out in Start-up mode Fail-safe mode; wake-up detected RSTN driven LOW internally but RSTN pin remains HIGH RSTN driven HIGH internally but RSTN pin remains LOW INTN = 0 0.45 x NWP 0.55 x NWP 1.1 x NWP input port filter time cyclic sense sample setup time VBAT42 = 5 V to 27 V VBAT42 = 27 V to 52 V V3C = 11 or 10; see Figure 13 5 30 310 120 250 390 s s s 14 28 345 345 18 36 423 423 ms ms s s tWD(LTP) 0.9 x NWP - tWD(init) Fail-safe mode tret watchdog initializing period retention time 229 - 283 ms 1.3 1.5 1.7 s Reset output; pin RSTN tRSTN(CHT) tRSTN(CLT) tRSTN(INT) clamped HIGH time, pin RSTN clamped LOW time, pin RSTN interrupt monitoring time 115 229 229 141 283 283 ms ms ms UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 64 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Table 27. Dynamic characteristics[1] ...continued Tvj = -40 C to + 150 C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 VBAT14 - 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. Symbol tRSTNL Parameter reset lengthening time Conditions after internal or external reset has been released; RLC = 0 after internal or external reset has been released; RLC =1 Interrupt output; pin INTN tINTN Oscillator fosc oscillator input frequency 460.8 512 563.2 kHz interrupt release after SPI has read out the Interrupt register 2 s Min 0.9 18 Typ Max 1.1 22 Unit ms ms [1] All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at Tamb = 125 C on wafer level (pretesting). Cased products are 100 % tested at Tamb = 25 C (final testing). Both pretesting and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. SPI timing is guaranteed for VBAT42 voltages down to 5 V. For VBAT42 voltages down to 4.5 V the guaranteed SPI timing values double, so at these lower voltages a lower maximum SPI communication speed must be observed. tbit = selected bit time, depends on LSC-bit; 50 s or 96 s (20 kbit/s or 10.4 kbit/s respectively); bus load conditions (R1/R2/C1): 1 k/1 k/10 nF; 1 k/1 k/6.8 nF; 1 k/open/1 nF; see Figure 25 and Figure 26. [2] [3] [4] t bus ( rec ) ( min ) 1, 3 = -----------------------------2 x t bit t bus ( rec ) ( max ) 2, 4 = ------------------------------2 x tbit [5] VCC BAT42 32 BAT14 27 24 RTH RRTH 500 CCAN_L RCAN_L BAT VCC 22 CANL FAILURE GENERATION UJA1061 TXDC 13 21 CANH RRTL 500 RXDC 10 pF 14 19 23 GND RTL GND CCAN_H RCAN_H 001aad804 Fig 23. Timing test circuit for CAN transceiver UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 65 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip VTXDC 50 % 50 % VCANL 90 % 90 % 10 % 90 % 10 % 90 % 5V 3.6 V VCANH 10 % tt(rec-dom) 10 % tt(dom-rec) 1.4 V 0V 2.2 V -3.2 V Vdif(CANH-CANL) -5 V VRXDC tPHL 50 % tPLH 50 % mce636 Fig 24. Timing diagram CAN transceiver BAT42 RXDL 20 pF RTLIN SBC TXDL GND LIN R1 R2 C1 001aad179 Fig 25. Timing test circuit for LIN transceiver UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 66 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip tbit VTXDL tbit tbit tbus(dom)(max) VBAT42 tbus(rec)(min) Vth(reces)(max) LIN BUS signal Vth(dom)(max) Vth(reces)(min) Vth(dom)(min) thresholds of receiving node 1 thresholds of receiving node 2 tbus(dom)(min) receiving node 1 VRXDL1 tbus(rec)(max) tp(rx)f receiving node 2 VRXDL2 tp(rx)r tp(rx)r tp(rx)f 001aaa346 Fig 26. Timing diagram LIN transceiver SCS tlead Tcyc tSCKH tSCKL tlag tSSH SCK tsu th SDI X MSB tDOV LSB X floating SDO X MSB LSB floating 001aaf044 Fig 27. SPI timing UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 67 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 11. Test information 11.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 68 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 12. Package outline HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad SOT549-1 D E A X c y exposed die pad side HE vMA Z Dh 32 17 Eh pin 1 index A2 A1 (A3) A Lp L 1 e bp 16 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.30 0.19 c 0.20 0.09 D(1) 11.1 10.9 Dh 5.1 4.9 E(2) 6.2 6.0 Eh 3.6 3.4 e 0.65 HE 8.3 7.9 L 1 Lp 0.75 0.50 v 0.2 w 0.1 y 0.1 Z 0.78 0.48 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT549-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 03-04-07 05-11-02 Fig 28. Package outline SOT549-1 (HTSSOP32) UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 69 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 70 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 13.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 29) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 28 and 29 Table 28. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 29. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 29. UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 71 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 29. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 72 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 14. Revision history Table 30. Revision history Release date 20100309 Data sheet status Product data sheet Change notice Supersedes UJA1061_5 Document ID UJA1061_6 Modifications: * * * * * * 3.0 V version (UJA1061TW/3V0) discontinued Table 26: updated conditions for VO(reces) - CANL recessive output voltage Section 6.2.5: text of third paragraph revised Table 11: text of bit 4, V1CMC, revised Section 11.1: text revised Section 2.1: text revised Product data sheet Product data sheet Preliminary data sheet Objective data sheet Objective specification UJA1061_4 UJA1061_3 UJA1061_2 UJA1061_1 - UJA1061_5 UJA1061_4 UJA1061_3 UJA1061_2 (9397 750 14201) UJA1061_1 (9397 750 11708) 20071122 20070427 20060627 20051122 20040322 UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 73 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer's third party customer(s) (hereinafter both referred to as "Application"). It is customer's sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. (c) NXP B.V. 2010. All rights reserved. 15.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or UJA1061_6 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 06 -- 9 March 2010 74 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 75 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 17. Contents 1 2 2.1 2.2 2.3 2.4 2.5 3 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.1.1 6.6.2 6.6.2.1 6.6.2.2 6.6.3 6.7 6.7.1 6.7.1.1 6.7.1.2 6.7.1.3 6.7.1.4 6.7.2 6.7.3 6.7.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 2 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 2 Power management . . . . . . . . . . . . . . . . . . . . . 3 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Fail-safe system controller . . . . . . . . . . . . . . . . 7 Start-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Restart mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Fail-safe mode . . . . . . . . . . . . . . . . . . . . . . . . . 9 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 10 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 On-chip oscillator . . . . . . . . . . . . . . . . . . . . . . 12 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Watchdog start-up behavior . . . . . . . . . . . . . . 13 Watchdog window behavior . . . . . . . . . . . . . . 13 Watchdog time-out behavior. . . . . . . . . . . . . . 14 Watchdog OFF behavior. . . . . . . . . . . . . . . . . 14 System reset. . . . . . . . . . . . . . . . . . . . . . . . . . 15 RSTN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 EN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 17 BAT14, BAT42 and SYSINH. . . . . . . . . . . . . . 17 SYSINH output . . . . . . . . . . . . . . . . . . . . . . . . 17 Voltage regulators V1 and V2 . . . . . . . . . . . . . 17 Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . 17 Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . 18 Switched battery output V3. . . . . . . . . . . . . . . 18 CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . 19 Mode control . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 20 On-line mode . . . . . . . . . . . . . . . . . . . . . . . . . 21 On-line Listen mode . . . . . . . . . . . . . . . . . . . . 21 Off-line mode . . . . . . . . . . . . . . . . . . . . . . . . . 21 CAN wake-up . . . . . . . . . . . . . . . . . . . . . . . . . 21 Termination control . . . . . . . . . . . . . . . . . . . . . 21 Bus, RXD and TXD failure detection . . . . . . . 22 6.7.4.1 6.7.4.2 6.7.4.3 6.8 6.8.1 6.8.1.1 6.8.1.2 6.8.2 6.8.3 6.8.4 6.8.5 6.8.6 6.8.6.1 6.8.6.2 6.8.6.3 6.9 6.10 6.11 6.12 6.13 6.13.1 6.13.2 6.13.3 6.13.4 6.13.5 6.13.6 6.13.7 6.13.8 6.13.9 6.13.10 6.13.11 6.13.12 6.14 6.14.1 6.14.2 7 8 9 10 11 11.1 12 TXDC dominant clamping . . . . . . . . . . . . . . . RXDC recessive clamping . . . . . . . . . . . . . . . GND shift detection . . . . . . . . . . . . . . . . . . . . LIN transceiver. . . . . . . . . . . . . . . . . . . . . . . . Mode control . . . . . . . . . . . . . . . . . . . . . . . . . Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . Off-line mode . . . . . . . . . . . . . . . . . . . . . . . . . LIN wake-up. . . . . . . . . . . . . . . . . . . . . . . . . . Termination control. . . . . . . . . . . . . . . . . . . . . LIN slope control . . . . . . . . . . . . . . . . . . . . . . LIN driver capability . . . . . . . . . . . . . . . . . . . . Bus and TXDL failure detection . . . . . . . . . . . TXDL dominant clamping. . . . . . . . . . . . . . . . LIN dominant clamping . . . . . . . . . . . . . . . . . LIN recessive clamping . . . . . . . . . . . . . . . . . Inhibit and limp-home output . . . . . . . . . . . . . Wake-up input . . . . . . . . . . . . . . . . . . . . . . . . Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . Temperature protection . . . . . . . . . . . . . . . . . SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . SPI register mapping . . . . . . . . . . . . . . . . . . . Register overview . . . . . . . . . . . . . . . . . . . . . Mode register . . . . . . . . . . . . . . . . . . . . . . . . . System Status register . . . . . . . . . . . . . . . . . . System Diagnosis register . . . . . . . . . . . . . . . Interrupt Enable register and Interrupt Enable Feedback register . . . . . . . . . . . . . . . Interrupt register. . . . . . . . . . . . . . . . . . . . . . . System Configuration register and System Configuration Feedback register . . . . . . . . . . Physical Layer Control register and Physical Layer Control Feedback register . . . . . . . . . . Special Mode register and Special Mode Feedback register . . . . . . . . . . . . . . . . . . . . . General Purpose registers and General Purpose Feedback registers . . . . . . . . . . . . . Register configurations at reset . . . . . . . . . . . Test modes. . . . . . . . . . . . . . . . . . . . . . . . . . . Software Development mode. . . . . . . . . . . . . Forced Normal mode . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Test information . . . . . . . . . . . . . . . . . . . . . . . Quality information . . . . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . 22 22 23 23 23 23 24 24 24 25 25 25 25 25 26 26 26 27 27 28 28 29 29 32 33 34 35 37 38 39 40 41 43 43 44 45 46 47 61 68 68 69 continued >> UJA1061_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 -- 9 March 2010 76 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 70 70 70 70 71 73 74 74 74 74 75 75 76 13 13.1 13.2 13.3 13.4 14 15 15.1 15.2 15.3 15.4 16 17 Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering . . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 March 2010 Document identifier: UJA1061_6 |
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